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-rw-r--r--src/soc/mediatek/common/include/soc/dramc_param_common.h3
-rw-r--r--src/soc/mediatek/common/include/soc/emi.h1
-rw-r--r--src/soc/mediatek/common/memory.c7
3 files changed, 9 insertions, 2 deletions
diff --git a/src/soc/mediatek/common/include/soc/dramc_param_common.h b/src/soc/mediatek/common/include/soc/dramc_param_common.h
index 7dd8bba5d8..a1fac9af85 100644
--- a/src/soc/mediatek/common/include/soc/dramc_param_common.h
+++ b/src/soc/mediatek/common/include/soc/dramc_param_common.h
@@ -92,7 +92,8 @@ enum SDRAM_VOLTAGE_TYPE {
struct ddr_base_info {
u32 config_dvfs; /* SDRAM_DVFS_FLAG */
struct sdram_info sdram;
- u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */
+ u16 lpddr_type;
+ u16 voltage_type; /* SDRAM_VOLTAGE_TYPE */
u32 support_ranks;
u64 rank_size[RANK_MAX];
struct emi_mdl emi_config;
diff --git a/src/soc/mediatek/common/include/soc/emi.h b/src/soc/mediatek/common/include/soc/emi.h
index 0070ec1bcd..313ccff30e 100644
--- a/src/soc/mediatek/common/include/soc/emi.h
+++ b/src/soc/mediatek/common/include/soc/emi.h
@@ -16,5 +16,6 @@ bool is_dvfs_enabled(void);
u32 get_ddr_geometry(void);
u32 get_ddr_type(void);
void init_dram_by_params(struct dramc_param *dparam);
+enum mem_chip_type map_to_lpddr_dram_type(uint16_t lpddr_type);
#endif /* SOC_MEDIATEK_COMMON_EMI_H */
diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c
index 089c6affac..f08b1d55cf 100644
--- a/src/soc/mediatek/common/memory.c
+++ b/src/soc/mediatek/common/memory.c
@@ -106,6 +106,11 @@ size_t mtk_dram_size(void)
return size;
}
+__weak enum mem_chip_type map_to_lpddr_dram_type(uint16_t lpddr_type)
+{
+ return MEM_CHIP_LPDDR4X;
+}
+
static void fill_dram_info(struct mem_chip_info *mc, const struct ddr_base_info *ddr)
{
unsigned int c, r;
@@ -118,7 +123,7 @@ static void fill_dram_info(struct mem_chip_info *mc, const struct ddr_base_info
for (r = 0; r < ddr->mrr_info.rank_nums; r++) {
entry->channel = c;
entry->rank = r;
- entry->type = MEM_CHIP_LPDDR4X;
+ entry->type = map_to_lpddr_dram_type(ddr->lpddr_type);
entry->channel_io_width = DQ_DATA_WIDTH_LP4;
entry->density_mbits = ddr->mrr_info.mr8_density[r] / CHANNEL_MAX /
(MiB / 8);