diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/mediatek/mt8188/devapc.c | 32 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/addressmap.h | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/devapc.h | 24 |
3 files changed, 55 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c index 6c585baf50..960c70ae07 100644 --- a/src/soc/mediatek/mt8188/devapc.c +++ b/src/soc/mediatek/mt8188/devapc.c @@ -114,14 +114,14 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-1", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-2", - NO_PROTECTION, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-3", NO_PROTECTION, FORBIDDEN15), /* 50 */ DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-4", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-5", - NO_PROTECTION, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-6", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-7", @@ -1616,6 +1616,8 @@ static void dump_fmem_ao(uintptr_t base) { printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_FMEM_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n", base, read32(getreg(base, DOM_REMAP_0_0))); + printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_FMEM_AO_BASE %#lx)MAS_DOM_1:%#x\n", + base, read32(getreg(base, MAS_DOM_1))); } static void dump_infra2_ao(uintptr_t base) @@ -1633,6 +1635,12 @@ static void dump_scp_master(uintptr_t base) read32(getreg(base, ONETIME_LOCK))); } +static void dump_sec_mfg_hyp(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_INFRA_BASE %#lx)INFRA_AO_SEC_MFG_HYP:%#x\n", + base, read32(getreg(base, 0))); +} + static void infra_init(uintptr_t base) { void *reg; @@ -1715,6 +1723,10 @@ static void peri_par_init(uintptr_t base) static void fmem_master_init(uintptr_t base) { + /* Master Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_1), + MFG_M0_DOM, DOMAIN_6); + /* * Domain Remap: TINYSYS to EMI (3-bit to 4-bit) * 1. DSP from 0 to 4 @@ -1770,6 +1782,18 @@ static void scp_master_init(uintptr_t base) write32(getreg(base, ONETIME_LOCK), 0x5); } +static void infra_sec_mfg_hyp_init(uintptr_t base) +{ + /* Set GPU protection mode */ + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), OSID0, MFG_NS_D6); + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), OSID1, MFG_NS_D6); + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), OSID2, MFG_NS_D6); + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), OSID3, MFG_NS_D6); + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), FM_EN, MFG_NS_D6); + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), SEC_EN, MFG_S_D6); + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), REMAP_EN, 1); +} + const struct devapc_init_ops devapc_init[] = { { DEVAPC_INFRA_AO_BASE, infra_init, dump_infra_ao_apc }, { DEVAPC_PERI_AO_BASE, peri_init, dump_peri_ao_apc }, @@ -1778,6 +1802,10 @@ const struct devapc_init_ops devapc_init[] = { { DEVAPC_FMEM_AO_BASE, fmem_master_init, dump_fmem_ao }, { DEVAPC_INFRA2_AO_BASE, infra2_master_init, dump_infra2_ao }, { SCP_CFG_BASE, scp_master_init, dump_scp_master }, + { INFRACFG_AO_BASE + INFRA_AO_SEC_MFG_HYP, + infra_sec_mfg_hyp_init, dump_sec_mfg_hyp }, + { SUB_INFRACFG_AO_BASE + INFRA_AO_SEC_MFG_HYP2, + infra_sec_mfg_hyp_init, dump_sec_mfg_hyp }, }; const size_t devapc_init_cnt = ARRAY_SIZE(devapc_init); diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h index 53e52146ea..b942a85d5d 100644 --- a/src/soc/mediatek/mt8188/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h @@ -55,6 +55,7 @@ enum { I2C6_DMA_BASE = IO_PHYS + 0x00220600, DEVAPC_INFRA2_AO_BASE = IO_PHYS + 0x00228000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, + SUB_INFRACFG_AO_BASE = IO_PHYS + 0x0030E000, INFRA_TRACKER_BASE = IO_PHYS + 0x00314000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000, SSPM_CFG_BASE = IO_PHYS + 0x00440000, diff --git a/src/soc/mediatek/mt8188/include/soc/devapc.h b/src/soc/mediatek/mt8188/include/soc/devapc.h index d71377c2b8..8765aded05 100644 --- a/src/soc/mediatek/mt8188/include/soc/devapc.h +++ b/src/soc/mediatek/mt8188/include/soc/devapc.h @@ -15,6 +15,7 @@ enum devapc_ao_offset { DOM_REMAP_0_1 = 0x00804, DOM_REMAP_2_0 = 0x00820, MAS_DOM_0 = 0x00900, + MAS_DOM_1 = 0x00904, MAS_SEC_0 = 0x00A00, AO_APC_CON = 0x00F00, }; @@ -26,6 +27,11 @@ enum scp_offset { ONETIME_LOCK = 0xA5104, }; +enum sub_infracfg_ao_mem_offset { + INFRA_AO_SEC_MFG_HYP = 0xFB4, + INFRA_AO_SEC_MFG_HYP2 = 0x68, +}; + /****************************************************************************** * STRUCTURE DEFINITION ******************************************************************************/ @@ -43,6 +49,11 @@ enum devapc_cfg_index { DEVAPC_DEBUGSYS_INDEX = 14, }; +enum mfg_dom { + MFG_S_D6 = 0x16, + MFG_NS_D6 = 0x6, +}; + /* PERM_ATTR MACRO */ #define DAPC_INFRA_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_16(__VA_ARGS__) } } #define DAPC_INFRA_AO_SYS1_ATTR(...) { { DAPC_PERM_ATTR_4(__VA_ARGS__) } } @@ -58,6 +69,7 @@ enum devapc_cfg_index { #define MOD_NO_IN_1_DEVAPC 16 #define DOMAIN_OFT 0x40 #define IDX_OFT 0x4 +#define MFG_HPY_OFT 0 /****************************************************************************** * Bit Field DEFINITION @@ -75,4 +87,16 @@ DEFINE_BITFIELD(SPM_DOM, 3, 0) /* 0 */ /* PERI_PAR */ DEFINE_BITFIELD(PCIE0_DOM, 27, 24) /* 19 */ +/* FMEM */ +DEFINE_BITFIELD(MFG_M0_DOM, 19, 16) /* 6 */ + +/* INFRACFG_AO SEC MFG HYP */ +DEFINE_BITFIELD(OSID0, 4, 0) +DEFINE_BITFIELD(OSID1, 9, 5) +DEFINE_BITFIELD(OSID2, 14, 10) +DEFINE_BITFIELD(OSID3, 19, 15) +DEFINE_BITFIELD(FM_EN, 24, 20) +DEFINE_BITFIELD(SEC_EN, 29, 25) +DEFINE_BIT(REMAP_EN, 31) + #endif /* SOC_MEDIATEK_MT8188_DEVAPC_H */ |