diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 7 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/registers/host_bridge.h | 1 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d533ca8a30..01dfcc4a7e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2459,6 +2459,13 @@ int discover_timC_write(ramctr_timing *ctrl) int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int channel, slotrank, lane; + /* Changing the write Vref is only supported on some Ivy Bridge SKUs */ + if (!IS_IVY_CPU(ctrl->cpu)) + return 0; + + if (!(pci_read_config32(HOST_BRIDGE, CAPID0_A) & CAPID_WRTVREF)) + return 0; + FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { lower[channel][slotrank][lane] = 0; upper[channel][slotrank][lane] = MAX_TIMC; diff --git a/src/northbridge/intel/sandybridge/registers/host_bridge.h b/src/northbridge/intel/sandybridge/registers/host_bridge.h index 4814b94b6f..95998714c8 100644 --- a/src/northbridge/intel/sandybridge/registers/host_bridge.h +++ b/src/northbridge/intel/sandybridge/registers/host_bridge.h @@ -52,6 +52,7 @@ #define CAPID_ECCDIS (1 << 25) #define CAPID_DDPCD (1 << 14) #define CAPID_PDCD (1 << 12) +#define CAPID_WRTVREF (1 << 1) #define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) #define CAPID0_B 0xe8 /* Capabilities Register B */ |