diff options
Diffstat (limited to 'src')
6 files changed, 51 insertions, 4 deletions
diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index b21291ea7d..a036fa5f1c 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_WIFI_GENERIC select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ESPI select ELOG diff --git a/src/mainboard/google/skyrim/romstage.c b/src/mainboard/google/skyrim/romstage.c new file mode 100644 index 0000000000..bd7af6a9cd --- /dev/null +++ b/src/mainboard/google/skyrim/romstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/platform_descriptors.h> + +void mb_pre_fspm(void) +{ + size_t base_num_gpios; + const struct soc_amd_gpio *base_gpios; + + /* Initialize PCIe reset. */ + variant_pcie_gpio_table(&base_gpios, &base_num_gpios); + + gpio_configure_pads(base_gpios, base_num_gpios); +} diff --git a/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc b/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc index 7c092e44c2..dc1c1fe1eb 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc @@ -1,5 +1,7 @@ bootblock-y += gpio.c +romstage-y += gpio.c + ramstage-y += gpio.c smm-y += gpio.c diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index c80286873a..ac9bd2beee 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -47,7 +47,12 @@ chip soc/amd/sabrina device pnp 0c09.0 alias chrome_ec on end end end - device ref gpp_bridge_0 on end # WLAN + device ref gpp_bridge_0 on # WLAN + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + device pci 00.0 on end + end + end device ref gpp_bridge_1 on end # SD device ref gpp_bridge_2 on end # WWAN device ref gpp_bridge_3 on end # NVMe diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index dd30475beb..f095651297 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -155,16 +155,37 @@ static const struct soc_amd_gpio sleep_gpio_table[] = { /* TODO: Fill sleep gpio configuration */ }; -/* Early GPIO configuration in bootblock */ +/* GPIO configuration in bootblock */ static const struct soc_amd_gpio bootblock_gpio_table[] = { - /* TODO: Fill bootblock gpio configuration */ + /* Enable WLAN */ + /* WLAN_DISABLE */ + PAD_GPO(GPIO_21, LOW), }; /* Early GPIO configuration */ static const struct soc_amd_gpio early_gpio_table[] = { - /* TODO: Fill early gpio configuration */ + /* WLAN_AUX_RESET_L (ACTIVE LOW) */ + PAD_GPO(GPIO_7, LOW), + /* Power on WLAN */ + /* EN_PP3300_WLAN */ + PAD_GPO(GPIO_9, HIGH), +}; + +/* PCIE_RST needs to be brought high before FSP-M runs */ +static const struct soc_amd_gpio pcie_gpio_table[] = { + /* Deassert all AUX_RESET lines & PCIE_RST */ + /* WLAN_AUX_RESET_L (ACTIVE LOW) */ + PAD_GPO(GPIO_7, HIGH), + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), }; +__weak void variant_pcie_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(pcie_gpio_table); + *gpio = pcie_gpio_table; +} + __weak void variant_base_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) { *size = ARRAY_SIZE(base_gpio_table); diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h index a99dd26c0d..0fa3491be5 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h @@ -34,4 +34,7 @@ void variant_sleep_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); /* This function provides GPIO settings for TPM i2c bus. */ void variant_tpm_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); +/* This function provides GPIO settings before PCIe enumeration. */ +void variant_pcie_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + #endif /* __BASEBOARD_VARIANTS_H__ */ |