8 files changed, 13 insertions, 17 deletions

diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c
index 678059f954..158601089e 100644
--- a/src/mainboard/google/veyron_brain/bootblock.c
+++ b/src/mainboard/google/veyron_brain/bootblock.c
@@ -70,7 +70,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
 
 	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c
index 678059f954..158601089e 100644
--- a/src/mainboard/google/veyron_danger/bootblock.c
+++ b/src/mainboard/google/veyron_danger/bootblock.c
@@ -70,7 +70,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
 
 	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c
index 985152bebc..43af3f5fa1 100644
--- a/src/mainboard/google/veyron_jerry/bootblock.c
+++ b/src/mainboard/google/veyron_jerry/bootblock.c
@@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
 
 	/* spi0 for chrome ec */
 	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
-	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
+	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
 
 	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c
index 985152bebc..43af3f5fa1 100644
--- a/src/mainboard/google/veyron_mighty/bootblock.c
+++ b/src/mainboard/google/veyron_mighty/bootblock.c
@@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
 
 	/* spi0 for chrome ec */
 	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
-	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
+	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
 
 	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
index 985152bebc..43af3f5fa1 100644
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ b/src/mainboard/google/veyron_pinky/bootblock.c
@@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
 
 	/* spi0 for chrome ec */
 	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
-	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
+	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
 
 	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c
index 135aece472..f59f8e941d 100644
--- a/src/mainboard/google/veyron_rialto/bootblock.c
+++ b/src/mainboard/google/veyron_rialto/bootblock.c
@@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
 
 	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c
index 985152bebc..43af3f5fa1 100644
--- a/src/mainboard/google/veyron_speedy/bootblock.c
+++ b/src/mainboard/google/veyron_speedy/bootblock.c
@@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
 
 	/* spi0 for chrome ec */
 	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
-	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
+	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
 
 	setup_chromeos_gpios();
 }
diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c
index aa70f3e0e5..a8d2be30fc 100644
--- a/src/soc/rockchip/rk3288/spi.c
+++ b/src/soc/rockchip/rk3288/spi.c
@@ -94,12 +94,8 @@ static void rockchip_spi_enable_chip(struct rockchip_spi *regs, int enable)
 
 static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz)
 {
-	unsigned short clk_div = 0;
-
-	/* Calculate clock divisor.  */
-	clk_div = SPI_SRCCLK_HZ / hz;
-	clk_div = (clk_div + 1) & 0xfffe;
-	assert((clk_div - 1) * hz == SPI_SRCCLK_HZ);
+	unsigned short clk_div = SPI_SRCCLK_HZ / hz;
+	assert(clk_div * hz == SPI_SRCCLK_HZ && !(clk_div & 1));
 	write32(&regs->baudr, clk_div);
 }