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-rw-r--r--src/soc/mediatek/mt8192/Makefile.inc1
-rw-r--r--src/soc/mediatek/mt8192/ddp.c198
-rw-r--r--src/soc/mediatek/mt8192/include/soc/addressmap.h13
-rw-r--r--src/soc/mediatek/mt8192/include/soc/ddp.h270
4 files changed, 482 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 157ada4dc6..23799663d7 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -38,6 +38,7 @@ romstage-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c
romstage-y += mt6359p.c
ramstage-y += ../common/auxadc.c
+ramstage-y += ../common/ddp.c ddp.c
ramstage-y += dpm.c
ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
ramstage-y += flash_controller.c
diff --git a/src/soc/mediatek/mt8192/ddp.c b/src/soc/mediatek/mt8192/ddp.c
new file mode 100644
index 0000000000..f03a9022c1
--- /dev/null
+++ b/src/soc/mediatek/mt8192/ddp.c
@@ -0,0 +1,198 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <edid.h>
+#include <soc/addressmap.h>
+#include <soc/ddp.h>
+
+static void disp_config_main_path_connection(void)
+{
+ /* ovl0->ovl0_2l */
+ write32(&mmsys_cfg->mmsys_ovl_mout_en,
+ (DISP_OVL0_GO_BG | DISP_OVL0_2L_GO_BLEND));
+ write32(&mmsys_cfg->ovl0_2l_mout_en, OVL0_MOUT_EN_DISP_RDMA0);
+ write32(&mmsys_cfg->rdma0_sel_in, RDMA0_SEL_IN_OVL0_2L);
+ write32(&mmsys_cfg->rdma0_sout_sel, RDMA0_SOUT_COLOR0);
+ write32(&mmsys_cfg->ccorr0_sout_sel, CCORR0_SOUT_AAL0);
+ write32(&mmsys_cfg->aal0_sel_in, AAL0_SEL_IN_CCORR0);
+ write32(&mmsys_cfg->dither0_mout_en, DITHER0_MOUT_DSI0);
+ write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0);
+}
+
+static void disp_config_main_path_mutex(void)
+{
+ write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH);
+
+ /* Clock source from DSI0 */
+ write32(&disp_mutex->mutex[0].ctl,
+ MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6));
+ write32(&disp_mutex->mutex[0].en, BIT(0));
+}
+
+static void ovl_bgclr_in_sel(u32 idx)
+{
+ setbits32(&disp_ovl[idx]->datapath_con, BIT(2));
+}
+
+static void ovl_layer_smi_id_en(u32 idx)
+{
+ printk(BIOS_INFO, "%s\n", __func__);
+
+ setbits32(&disp_ovl[idx]->datapath_con, BIT(0));
+}
+
+static void ccorr_config(u32 width, u32 height)
+{
+ struct disp_ccorr_regs *const regs = disp_ccorr;
+ int enable_relay = 0;
+
+ printk(BIOS_INFO, "%s\n", __func__);
+
+ write32(&regs->size, width << 16 | height);
+
+ if (enable_relay) {
+ setbits32(&regs->cfg, PQ_RELAY_MODE);
+ clrbits32(&regs->cfg, PQ_ENGINE_EN);
+ } else {
+ clrbits32(&regs->cfg, PQ_RELAY_MODE);
+ setbits32(&regs->cfg, PQ_ENGINE_EN);
+ }
+
+ write32(&regs->en, PQ_EN);
+}
+
+static void aal_config(u32 width, u32 height)
+{
+ struct disp_aal_regs *const regs = disp_aal;
+ int enable_relay = 1;
+
+ printk(BIOS_INFO, "%s\n", __func__);
+
+ write32(&regs->size, width << 16 | height);
+ write32(&regs->output_size, width << 16 | height);
+
+ if (enable_relay) {
+ setbits32(&regs->cfg, PQ_RELAY_MODE);
+ clrbits32(&regs->cfg, PQ_ENGINE_EN);
+ } else {
+ clrbits32(&regs->cfg, PQ_RELAY_MODE);
+ setbits32(&regs->cfg, PQ_ENGINE_EN);
+ }
+
+ write32(&regs->en, PQ_EN);
+}
+
+static void gamma_config(u32 width, u32 height)
+{
+ struct disp_gamma_regs *const regs = disp_gamma;
+ int enable_relay = 0;
+
+ printk(BIOS_INFO, "%s\n", __func__);
+
+ write32(&regs->size, width << 16 | height);
+
+ if (enable_relay)
+ setbits32(&regs->cfg, PQ_RELAY_MODE);
+ else
+ clrbits32(&regs->cfg, PQ_RELAY_MODE);
+
+ write32(&regs->en, PQ_EN);
+}
+
+static void postmask_config(u32 width, u32 height)
+{
+ struct disp_postmask_regs *const regs = disp_postmask;
+ int enable_relay = 1;
+
+ printk(BIOS_INFO, "%s\n", __func__);
+
+ write32(&regs->size, width << 16 | height);
+
+ if (enable_relay)
+ setbits32(&regs->cfg, PQ_RELAY_MODE);
+ else
+ clrbits32(&regs->cfg, PQ_RELAY_MODE);
+
+ write32(&regs->en, PQ_EN);
+}
+
+static void dither_config(u32 width, u32 height)
+{
+ struct disp_dither_regs *const regs = disp_dither;
+ int enable_relay = 1;
+
+ printk(BIOS_INFO, "%s\n", __func__);
+
+ write32(&regs->size, width << 16 | height);
+
+ if (enable_relay)
+ setbits32(&regs->cfg, PQ_RELAY_MODE);
+ else
+ clrbits32(&regs->cfg, PQ_RELAY_MODE);
+
+ write32(&regs->en, PQ_EN);
+}
+
+
+static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh)
+{
+ u32 idx = 0;
+ u32 pixel_clk = width * height * vrefresh;
+
+ printk(BIOS_INFO, "%s\n", __func__);
+
+ for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) {
+ ovl_set_roi(idx, width, height, idx ? 0 : 0xff0000ff);
+ ovl_layer_smi_id_en(idx);
+ }
+
+ rdma_config(width, height, pixel_clk, 5 * KiB);
+ color_start(width, height);
+ ccorr_config(width, height);
+ aal_config(width, height);
+ gamma_config(width, height);
+ postmask_config(width, height);
+ dither_config(width, height);
+ disp_config_main_path_connection();
+ disp_config_main_path_mutex();
+}
+
+static void disp_clock_on(void)
+{
+ clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
+
+ clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_ALL);
+
+ clrbits32(&mmsys_cfg->mmsys_cg_con2, CG_CON2_DISP_ALL);
+}
+
+void mtk_ddp_init(void)
+{
+ disp_clock_on();
+ /* Turn off M4U port. */
+ write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0);
+}
+
+void mtk_ddp_mode_set(const struct edid *edid)
+{
+ u32 fmt = OVL_INFMT_RGBA8888;
+ u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+ u32 width = edid->mode.ha;
+ u32 height = edid->mode.va;
+ u32 vrefresh = edid->mode.refresh;
+
+ printk(BIOS_INFO, "%s display resolution: %dx%d@%d bpp %d\n",
+ __func__, width, height, vrefresh, bpp);
+
+ if (!vrefresh) {
+ vrefresh = 60;
+ printk(BIOS_INFO, "%s invalid vrefresh %d\n",
+ __func__, vrefresh);
+ }
+
+ main_disp_path_setup(width, height, vrefresh);
+ rdma_start();
+ ovl_layer_config(fmt, bpp, width, height);
+ ovl_bgclr_in_sel(1);
+}
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h
index 6cee8f3897..ab3bd75125 100644
--- a/src/soc/mediatek/mt8192/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h
@@ -60,6 +60,19 @@ enum {
IOCFG_TL_BASE = IO_PHYS + 0x01F30000,
MSDC0_TOP_BASE = IO_PHYS + 0x01F50000,
MSDC0_BASE = IO_PHYS + 0x01F60000,
+ MMSYS_BASE = IO_PHYS + 0x04000000,
+ DISP_MUTEX_BASE = IO_PHYS + 0x04001000,
+ SMI_BASE = IO_PHYS + 0x04002000,
+ SMI_LARB0 = IO_PHYS + 0x04003000,
+ DISP_OVL0_BASE = IO_PHYS + 0x04005000, /* ovl0 */
+ DISP_OVL1_BASE = IO_PHYS + 0x04006000, /* ovl0_2l */
+ DISP_RDMA0_BASE = IO_PHYS + 0x04007000,
+ DISP_COLOR0_BASE = IO_PHYS + 0x04009000,
+ DISP_CCORR0_BASE = IO_PHYS + 0x0400A000,
+ DISP_AAL0_BASE = IO_PHYS + 0x0400B000,
+ DISP_GAMMA0_BASE = IO_PHYS + 0x0400C000,
+ DISP_POSTMASK0_BASE = IO_PHYS + 0x0400D000,
+ DISP_DITHER0_BASE = IO_PHYS + 0x0400E000,
DSI0_BASE = IO_PHYS + 0x04010000,
};
diff --git a/src/soc/mediatek/mt8192/include/soc/ddp.h b/src/soc/mediatek/mt8192/include/soc/ddp.h
new file mode 100644
index 0000000000..dba97f0772
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/ddp.h
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MT8183_SOC_DDP_H_
+#define _MT8183_SOC_DDP_H_
+
+#include <soc/addressmap.h>
+#include <soc/ddp_common.h>
+#include <types.h>
+
+#define MAIN_PATH_OVL_NR 2
+
+struct mmsys_cfg_regs {
+ u32 reserved_0x000[64]; /* 0x000 */
+ u32 mmsys_cg_con0; /* 0x100 */
+ u32 mmsys_cg_set0; /* 0x104 */
+ u32 mmsys_cg_clr0; /* 0x108 */
+ u32 reserved_0x10C; /* 0x10C */
+ u32 mmsys_cg_con1; /* 0x110 */
+ u32 mmsys_cg_set1; /* 0x114 */
+ u32 mmsys_cg_clr1; /* 0x118 */
+ u32 reserved_0x11C[33]; /* 0x11C */
+ u32 mmsys_cg_con2; /* 0x1A0 */
+ u32 mmsys_cg_set2; /* 0x1A4 */
+ u32 mmsys_cg_clr2; /* 0x1A8 */
+ u32 reserved_0x1AC[853]; /* 0x1AC */
+ u32 reserved_0xF00; /* 0xF00 */
+ u32 mmsys_ovl_mout_en; /* 0xF04 */
+ u32 reserved_0xF08; /* 0xF08 */
+ u32 reserved_0xF0C; /* 0xF0C */
+ u32 reserved_0xF10; /* 0xF10 */
+ u32 reserved_0xF14; /* 0xF14 */
+ u32 ovl0_2l_mout_en; /* 0xF18 */
+ u32 ovl0_mout_en; /* 0xF1C */
+ u32 reserved_0xF20; /* 0xF20 */
+ u32 reserved_0xF24; /* 0xF24 */
+ u32 reserved_0xF28; /* 0xF28 */
+ u32 rdma0_sel_in; /* 0xF2C */
+ u32 rdma0_sout_sel; /* 0xF30 */
+ u32 ccorr0_sout_sel; /* 0xF34 */
+ u32 aal0_sel_in; /* 0xF38 */
+ u32 dither0_mout_en; /* 0xF3C*/
+ u32 dsi0_sel_in; /* 0xF40*/
+};
+
+check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100);
+check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110);
+check_member(mmsys_cfg_regs, mmsys_cg_con2, 0x1A0);
+check_member(mmsys_cfg_regs, mmsys_ovl_mout_en, 0xF04);
+check_member(mmsys_cfg_regs, ovl0_2l_mout_en, 0xF18);
+check_member(mmsys_cfg_regs, dsi0_sel_in, 0xF40);
+static struct mmsys_cfg_regs *const mmsys_cfg =
+ (void *)MMSYS_BASE;
+
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON0
+ Configures free-run clock gating 0
+ 0: Enable clock
+ 1: Clock gating */
+enum {
+ CG_CON0_DISP_MUTEX0 = BIT(0),
+ CG_CON0_DISPSYS_CONFIG = BIT(1),
+ CG_CON0_DISP_OVL0 = BIT(2),
+ CG_CON0_DISP_RDMA0 = BIT(3),
+ CG_CON0_DISP_OVL0_2L = BIT(4),
+ CG_CON0_DISP_AAL0 = BIT(8),
+ CG_CON0_DISP_CCORR0 = BIT(9),
+ CG_CON0_DISP_DITHER0 = BIT(10),
+ CG_CON0_SMI_INFRA = BIT(11),
+ CG_CON0_DISP_GAMMA0 = BIT(12),
+ CG_CON0_DISP_POSTMASK0 = BIT(13),
+ CG_CON0_DISP_DSI0 = BIT(15),
+ CG_CON0_DISP_COLOR0 = BIT(16),
+ CG_CON0_SMI_COMMON = BIT(17),
+
+ CG_CON0_SMI_GALS = BIT(27),
+ CG_CON0_DISP_ALL = CG_CON0_SMI_INFRA |
+ CG_CON0_SMI_COMMON |
+ CG_CON0_SMI_GALS |
+ CG_CON0_DISP_MUTEX0 |
+ CG_CON0_DISPSYS_CONFIG |
+ CG_CON0_DISP_OVL0 |
+ CG_CON0_DISP_RDMA0 |
+ CG_CON0_DISP_OVL0_2L |
+ CG_CON0_DISP_AAL0 |
+ CG_CON0_DISP_CCORR0 |
+ CG_CON0_DISP_DITHER0 |
+ CG_CON0_DISP_GAMMA0 |
+ CG_CON0_DISP_POSTMASK0 |
+ CG_CON0_DISP_DSI0 |
+ CG_CON0_DISP_COLOR0,
+ CG_CON0_ALL = 0xffffffff
+};
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON1
+ Configures free-run clock gating 1
+ 0: Enable clock
+ 1: Clock gating */
+enum {
+ CG_CON1_SMI_IOMMU = BIT(0),
+ CG_CON1_DISP_ALL = CG_CON1_SMI_IOMMU,
+ CG_CON1_ALL = 0xffffffff
+};
+
+enum {
+ CG_CON2_DSI_DSI0 = BIT(0),
+ CG_CON2_DPI_DPI0 = BIT(8),
+ CG_CON2_MM_26MHZ = BIT(24),
+ CG_CON2_DISP_ALL = CG_CON2_DSI_DSI0 |
+ CG_CON2_MM_26MHZ,
+ CG_CON2_ALL = 0xffffffff
+};
+
+
+enum {
+ DISP_OVL0_GO_BLEND = BIT(0),
+ DISP_OVL0_GO_BG = BIT(1),
+ DISP_OVL0_2L_GO_BLEND = BIT(2),
+ DISP_OVL0_2L_GO_BG = BIT(3),
+ OVL0_MOUT_EN_DISP_RDMA0 = BIT(0),
+ DITHER0_MOUT_DSI0 = BIT(0),
+};
+
+enum {
+ RDMA0_SEL_IN_OVL0_2L = 0x3,
+ RDMA0_SOUT_COLOR0 = 0x1,
+ CCORR0_SOUT_AAL0 = 0x1,
+ AAL0_SEL_IN_CCORR0 = 0x1,
+ DSI0_SEL_IN_DITHER0 = 0x1,
+};
+
+struct disp_mutex_regs {
+ u32 inten;
+ u32 intsta;
+ u32 reserved0[6];
+ struct {
+ u32 en;
+ u32 dummy;
+ u32 rst;
+ u32 ctl;
+ u32 mod;
+ u32 reserved[3];
+ } mutex[12];
+};
+
+static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE;
+
+enum {
+ MUTEX_MOD_DISP_OVL0 = BIT(0),
+ MUTEX_MOD_DISP_OVL0_2L = BIT(1),
+ MUTEX_MOD_DISP_RDMA0 = BIT(2),
+ MUTEX_MOD_DISP_COLOR0 = BIT(4),
+ MUTEX_MOD_DISP_CCORR0 = BIT(5),
+ MUTEX_MOD_DISP_AAL0 = BIT(6),
+ MUTEX_MOD_DISP_GAMMA0 = BIT(7),
+ MUTEX_MOD_DISP_POSTMASK0 = BIT(8),
+ MUTEX_MOD_DISP_DITHER0 = BIT(9),
+ MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 |
+ MUTEX_MOD_DISP_OVL0_2L |
+ MUTEX_MOD_DISP_RDMA0 |
+ MUTEX_MOD_DISP_COLOR0 |
+ MUTEX_MOD_DISP_CCORR0 |
+ MUTEX_MOD_DISP_AAL0 |
+ MUTEX_MOD_DISP_GAMMA0 |
+ MUTEX_MOD_DISP_POSTMASK0 |
+ MUTEX_MOD_DISP_DITHER0,
+};
+
+enum {
+ MUTEX_SOF_SINGLE_MODE = 0,
+ MUTEX_SOF_DSI0 = 1,
+ MUTEX_SOF_DPI0 = 2,
+};
+
+struct disp_ccorr_regs {
+ u32 en;
+ u32 reset;
+ u32 inten;
+ u32 intsta;
+ u32 status;
+ u32 reserved0[3];
+ u32 cfg;
+ u32 reserved1[3];
+ u32 size;
+ u32 reserved2[27];
+ u32 shadow;
+};
+check_member(disp_ccorr_regs, shadow, 0xA0);
+
+struct disp_gamma_regs {
+ u32 en;
+ u32 reset;
+ u32 inten;
+ u32 intsta;
+ u32 status;
+ u32 reserved0[3];
+ u32 cfg;
+ u32 reserved1[3];
+ u32 size;
+};
+check_member(disp_gamma_regs, size, 0x30);
+
+struct disp_aal_regs {
+ u32 en;
+ u32 reset;
+ u32 inten;
+ u32 intsta;
+ u32 status;
+ u32 reserved0[3];
+ u32 cfg;
+ u32 reserved1[3];
+ u32 size;
+ u32 reserved2[47];
+ u32 shadow;
+ u32 reserved3[249];
+ u32 output_size;
+};
+check_member(disp_aal_regs, shadow, 0xF0);
+check_member(disp_aal_regs, output_size, 0x4D8);
+
+struct disp_postmask_regs {
+ u32 en;
+ u32 reset;
+ u32 inten;
+ u32 intsta;
+ u32 reserved0[4];
+ u32 cfg;
+ u32 reserved1[3];
+ u32 size;
+};
+check_member(disp_postmask_regs, size, 0x30);
+
+struct disp_dither_regs {
+ u32 en;
+ u32 reset;
+ u32 inten;
+ u32 intsta;
+ u32 status;
+ u32 reserved0[3];
+ u32 cfg;
+ u32 reserved1[3];
+ u32 size;
+ u32 reserved2[51];
+ u32 shadow;
+};
+check_member(disp_dither_regs, shadow, 0x100);
+
+enum {
+ PQ_EN = BIT(0),
+ PQ_RELAY_MODE = BIT(0),
+ PQ_ENGINE_EN = BIT(1),
+};
+
+static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE;
+
+static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE;
+
+static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE;
+
+static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE;
+
+static struct disp_postmask_regs *const disp_postmask = (void *)DISP_POSTMASK0_BASE;
+
+enum {
+ SMI_LARB_PORT_L0_OVL_RDMA0 = 0x388,
+};
+
+void mtk_ddp_init(void);
+void mtk_ddp_mode_set(const struct edid *edid);
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 12:42:14 +0000