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-rw-r--r--src/soc/intel/baytrail/acpi/globalnvs.asl1
-rw-r--r--src/soc/intel/baytrail/include/soc/nvs.h3
-rw-r--r--src/soc/intel/quark/include/soc/nvs.h4
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/globalnvs.asl3
-rw-r--r--src/southbridge/intel/bd82x6x/include/soc/nvs.h6
-rw-r--r--src/southbridge/intel/i82801gx/acpi/globalnvs.asl2
-rw-r--r--src/southbridge/intel/i82801gx/include/soc/nvs.h4
-rw-r--r--src/southbridge/intel/i82801ix/acpi/globalnvs.asl3
-rw-r--r--src/southbridge/intel/i82801ix/include/soc/nvs.h4
-rw-r--r--src/southbridge/intel/i82801jx/acpi/globalnvs.asl2
-rw-r--r--src/southbridge/intel/i82801jx/include/soc/nvs.h4
-rw-r--r--src/southbridge/intel/ibexpeak/acpi/globalnvs.asl3
-rw-r--r--src/southbridge/intel/ibexpeak/include/soc/nvs.h4
-rw-r--r--src/southbridge/intel/lynxpoint/acpi/globalnvs.asl3
-rw-r--r--src/southbridge/intel/lynxpoint/include/soc/nvs.h4
15 files changed, 48 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index cffb2241f0..c73b7a7b3f 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -25,6 +25,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TLVL, 8, /* 0x13 - Throttle Level */
PPCM, 8, /* 0x14 - Maximum P-state usable by OS */
PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */
+ GPEI, 32, /* 0x19 - GPE Wake Source */
/* Device Config */
Offset (0x20),
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index 9fb0822b9b..a068d1edd4 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -25,7 +25,8 @@ struct __packed global_nvs {
u8 tlvl; /* 0x13 - Throttle Level */
u8 ppcm; /* 0x14 - Maximum P-state usable by OS */
u32 pm1i; /* 0x15 - System Wake Source - PM1 Index */
- u8 rsvd1[7];
+ u32 gpei; /* 0x19 - GPE Wake Source */
+ u8 rsvd1[3];
/* Device Config */
u8 s5u0; /* 0x20 - Enable USB0 in S5 */
diff --git a/src/soc/intel/quark/include/soc/nvs.h b/src/soc/intel/quark/include/soc/nvs.h
index fee0e42a7d..64378cce3d 100644
--- a/src/soc/intel/quark/include/soc/nvs.h
+++ b/src/soc/intel/quark/include/soc/nvs.h
@@ -8,6 +8,10 @@
struct __packed global_nvs {
uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
uint8_t pwrs; /* 0x4 - Power state (AC = 1) */
+
+ /* Required for future unified acpi_save_wake_source. */
+ uint32_t pm1i;
+ uint32_t gpei;
};
#endif /* SOC_INTEL_QUARK_NVS_H */
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index e873f55375..25dcfe0ffe 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -100,6 +100,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xb2),
XHCI, 8,
+ PM1I, 32, // System Wake Source - PM1 Index
+ GPEI, 32, // GPE Wake Source
+
Offset (0xf5),
TPIQ, 8, // 0xf5 - trackpad IRQ value
CBMC, 32,
diff --git a/src/southbridge/intel/bd82x6x/include/soc/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
index 969d59209b..1c33b0cd73 100644
--- a/src/southbridge/intel/bd82x6x/include/soc/nvs.h
+++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
@@ -97,7 +97,11 @@ struct __packed global_nvs {
u8 rsvd11[6];
/* XHCI */
u8 xhci;
- u8 rsvd12[65];
+
+ /* Required for future unified acpi_save_wake_source. */
+ u32 pm1i;
+ u32 gpei;
+ u8 rsvd12[57];
u8 tpiq; /* 0xf5 - trackpad IRQ value */
u32 cbmc;
diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
index 1e3889b4f5..a3b15b68d7 100644
--- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
@@ -101,4 +101,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
DOCK, 8, // 0xf0 - Docking Status
BTEN, 8, // 0xf1 - Bluetooth Enable
CBMC, 32,
+ PM1I, 32, // System Wake Source - PM1 Index
+ GPEI, 32, // GPE Wake Source
}
diff --git a/src/southbridge/intel/i82801gx/include/soc/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h
index b2a6baa7e8..933921c3f4 100644
--- a/src/southbridge/intel/i82801gx/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h
@@ -98,6 +98,10 @@ struct __packed global_nvs {
u8 bten;
u32 cbmc;
+
+ /* Required for future unified acpi_save_wake_source. */
+ u32 pm1i;
+ u32 gpei;
};
#endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */
diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
index d2af885b0e..f408a8c53a 100644
--- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
@@ -103,4 +103,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
DOCK, 8, // 0xf0 - Docking Status
BTEN, 8, // 0xf1 - Bluetooth Enable
CBMC, 32,
+ PM1I, 32, // System Wake Source - PM1 Index
+ GPEI, 32, // GPE Wake Source
+
}
diff --git a/src/southbridge/intel/i82801ix/include/soc/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h
index 2d4980bec3..3c9aac90a2 100644
--- a/src/southbridge/intel/i82801ix/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h
@@ -98,6 +98,10 @@ struct __packed global_nvs {
u8 bten;
u32 cbmc;
+
+ /* Required for future unified acpi_save_wake_source. */
+ u32 pm1i;
+ u32 gpei;
};
#endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */
diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
index d2af885b0e..264b52a3b0 100644
--- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
@@ -103,4 +103,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
DOCK, 8, // 0xf0 - Docking Status
BTEN, 8, // 0xf1 - Bluetooth Enable
CBMC, 32,
+ PM1I, 32, // System Wake Source - PM1 Index
+ GPEI, 32, // GPE Wake Source
}
diff --git a/src/southbridge/intel/i82801jx/include/soc/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h
index 4325a8c1ee..54c4a2c7c4 100644
--- a/src/southbridge/intel/i82801jx/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h
@@ -97,6 +97,10 @@ struct __packed global_nvs {
u8 bten;
u32 cbmc;
+
+ /* Required for future unified acpi_save_wake_source. */
+ u32 pm1i;
+ u32 gpei;
};
#endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */
diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
index 949da74d8c..46c6f4f958 100644
--- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
+++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
@@ -100,6 +100,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xb2),
XHCI, 8,
CBMC, 32,
+ PM1I, 32, // System Wake Source - PM1 Index
+ GPEI, 32, // GPE Wake Source
+
}
/* Set flag to enable USB charging in S3 */
diff --git a/src/southbridge/intel/ibexpeak/include/soc/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
index 5ce88a68b1..03897cd4b7 100644
--- a/src/southbridge/intel/ibexpeak/include/soc/nvs.h
+++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
@@ -100,6 +100,10 @@ struct __packed global_nvs {
u8 xhci;
u32 cbmc;
+
+ /* Required for future unified acpi_save_wake_source. */
+ u32 pm1i;
+ u32 gpei;
};
#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */
diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
index 979e084161..1b06beb7b6 100644
--- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
@@ -93,6 +93,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xa0),
CBMC, 32, // 0xa0 - coreboot mem console pointer
+
+ PM1I, 32, // System Wake Source - PM1 Index
+ GPEI, 32, // GPE Wake Source
}
/* Set flag to enable USB charging in S3 */
diff --git a/src/southbridge/intel/lynxpoint/include/soc/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
index 17ded13589..7db206e6e9 100644
--- a/src/southbridge/intel/lynxpoint/include/soc/nvs.h
+++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
@@ -73,6 +73,10 @@ struct __packed global_nvs {
u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */
u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */
u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */
+
+ /* Required for future unified acpi_save_wake_source. */
+ u32 pm1i;
+ u32 gpei;
};
#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */