5 files changed, 1069 insertions, 0 deletions

diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index 477a5d7706..2704305026 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -10,9 +10,11 @@ bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pcd.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += espi.c
+bootblock-y += gpio.c
 bootblock-y += soc_info.c
 
 romstage-y += espi.c
+romstage-y += gpio.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
 romstage-y += reset.c
diff --git a/src/soc/intel/pantherlake/gpio.c b/src/soc/intel/pantherlake/gpio.c
new file mode 100644
index 0000000000..581607d4e3
--- /dev/null
+++ b/src/soc/intel/pantherlake/gpio.c
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <intelblocks/gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <soc/pmc.h>
+
+static const struct reset_mapping rst_map[] = {
+	{ .logical = PAD_RESET(PWROK), .chipset = 0U << 30 },
+	{ .logical = PAD_RESET(DEEP), .chipset = 1U << 30 },
+	{ .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 },
+	{ .logical = PAD_RESET(GLBRST), .chipset = 3U << 30 },
+};
+
+/*
+ * The GPIO pinctrl driver for Panther Lake on Linux expects 32 GPIOs per pad
+ * group, regardless of whether or not there is a physical pad for each
+ * exposed GPIO number.
+ *
+ * This results in the OS having a sparse GPIO map, and devices that need
+ * to export an ACPI GPIO must use the OS expected number.
+ *
+ * Not all pins are usable as GPIO and those groups do not have a pad base.
+ */
+static const struct pad_group ptl_community0_groups[] = {
+	INTEL_GPP_BASE(GPP_V00, GPP_V00, GPP_RST_B, 0),			/* GPP_V */
+	INTEL_GPP_BASE(GPP_V00, GPP_C00, GPP_C23, 32),			/* GPP_C */
+};
+
+static const struct pad_group ptl_community1_groups[] = {
+	INTEL_GPP_BASE(GPP_F00, GPP_F00, GPP_GSPI0_CLK_LOOPBK, 0),	/* GPP_F */
+	INTEL_GPP_BASE(GPP_F00, GPP_E00, GPP_THC0_GSPI_CLK_LPBK, 32),	/* GPP_E */
+};
+
+static const struct pad_group ptl_community3_groups[] = {
+	INTEL_GPP(GPP_EPD_ON, GPP_EPD_ON, GPP_DDSP_HPDALV),		/* GPP_CPUJTAG */
+	INTEL_GPP_BASE(GPP_EPD_ON, GPP_H00, GPP_ISHI3C1_CLK_LPBK, 32),	/* GPP_H */
+	INTEL_GPP_BASE(GPP_EPD_ON, GPP_A00, GPP_SPI0_CLK_LOOPBK, 64),	/* GPP_A */
+	INTEL_GPP(GPP_EPD_ON, GPP_VGPIO3_USB0, GPP_VGPIO3_THC3),	/* GPP_VGPIO_3*/
+};
+
+static const struct pad_group ptl_community4_groups[] = {
+	INTEL_GPP_BASE(GPP_S00, GPP_S00, GPP_S07, 0),			/* GPP_S */
+};
+
+static const struct pad_group ptl_community5_groups[] = {
+	INTEL_GPP_BASE(GPP_B00, GPP_B00, GPP_ISHI3C0_CLK_LPBK, 0),	/* GPP_B */
+	INTEL_GPP_BASE(GPP_B00, GPP_D00, GPP_D25, 32),			/* GPP_D */
+	INTEL_GPP(GPP_B00, GPP_VGPIO0, GPP_VGPIO47),			/* GPP_VGPIO */
+};
+
+static const struct pad_community ptl_communities[] = {
+	[COMM_0] = { /* GPP V,C */
+		.port = PID_GPIOCOM0,
+		.first_pad = COM0_GRP_PAD_START,
+		.last_pad = COM0_GRP_PAD_END,
+		.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_V_C",
+		.acpi_path = "\\_SB.PCI0.GPI0",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = ptl_community0_groups,
+		.num_groups = ARRAY_SIZE(ptl_community0_groups),
+	},
+	[COMM_1] = { /* GPP: F, E */
+		.port = PID_GPIOCOM1,
+		.first_pad = COM1_GRP_PAD_START,
+		.last_pad = COM1_GRP_PAD_END,
+		.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_F_E",
+		.acpi_path = "\\_SB.PCI0.GPI1",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = ptl_community1_groups,
+		.num_groups = ARRAY_SIZE(ptl_community1_groups),
+	},
+	[COMM_3] = { /* GPP: CPUJTAG, H, A, VGPIO3 */
+		.port = PID_GPIOCOM3,
+		.first_pad = COM3_GRP_PAD_START,
+		.last_pad = COM3_GRP_PAD_END,
+		.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_CPUJTAG_H_A_VGPIO3",
+		.acpi_path = "\\_SB.PCI0.GPI3",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = ptl_community3_groups,
+		.num_groups = ARRAY_SIZE(ptl_community3_groups),
+	},
+	[COMM_4] = { /* GPP: S */
+		.port = PID_GPIOCOM4,
+		.first_pad = COM4_GRP_PAD_START,
+		.last_pad = COM4_GRP_PAD_END,
+		.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_S",
+		.acpi_path = "\\_SB.PCI0.GPI4",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = ptl_community4_groups,
+		.num_groups = ARRAY_SIZE(ptl_community4_groups),
+	},
+	[COMM_5] = { /* GPP: B, D, VGPIO */
+		.port = PID_GPIOCOM5,
+		.first_pad = COM5_GRP_PAD_START,
+		.last_pad = COM5_GRP_PAD_END,
+		.num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.pad_cfg_lock_offset = PAD_CFG_LOCK_REG_0,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+		.gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_B_D_VGPIO",
+		.acpi_path = "\\_SB.PCI0.GPI5",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = ptl_community5_groups,
+		.num_groups = ARRAY_SIZE(ptl_community5_groups),
+	}
+};
+
+const struct pad_community *soc_gpio_get_community(size_t *num_communities)
+{
+	*num_communities = ARRAY_SIZE(ptl_communities);
+	return ptl_communities;
+}
+
+const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
+{
+	static const struct pmc_to_gpio_route routes[] = {
+		{ PMC_GPP_V, GPP_V },
+		{ PMC_GPP_C, GPP_C },
+		{ PMC_GPP_F, GPP_F },
+		{ PMC_GPP_E, GPP_E },
+		{ PMC_GPP_A, GPP_A },
+		{ PMC_GPP_H, GPP_H },
+		{ PMC_GPP_VGPIO, GPP_VGPIO },
+		{ PMC_GPP_B, GPP_B },
+		{ PMC_GPP_D, GPP_D },
+		{ PMC_GPP_S, GPP_S },
+	};
+	*num = ARRAY_SIZE(routes);
+	return routes;
+}
diff --git a/src/soc/intel/pantherlake/include/soc/gpio.h b/src/soc/intel/pantherlake/include/soc/gpio.h
new file mode 100644
index 0000000000..d7b562f173
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/gpio.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_GPIO_H_
+#define _SOC_PANTHERLAKE_GPIO_H_
+
+#include <soc/gpio_defs.h>
+#include <intelblocks/gpio.h>
+
+#define CROS_GPIO_NAME           "INTC10BC"
+#define CROS_GPIO_DEVICE0_NAME   "INTC10BC:00"
+#define CROS_GPIO_DEVICE1_NAME   "INTC10BC:01"
+#define CROS_GPIO_DEVICE2_NAME   "INTC10BC:02"
+#define CROS_GPIO_DEVICE3_NAME   "INTC10BC:03"
+#define CROS_GPIO_DEVICE4_NAME   "INTC10BC:04"
+
+#define ACPI_GPIO_CID "INTC105F"
+#define ACPI_GPIO_HID CROS_GPIO_NAME
+
+#define GPP_COMM0_NAME "Community 0"
+#define GPP_COMM1_NAME "Community 1"
+#define GPP_COMM3_NAME "Community 3"
+#define GPP_COMM4_NAME "Community 4"
+#define GPP_COMM5_NAME "Community 5"
+
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \
+	MISCCFG_GPPGCBDPCGEN | MISCCFG_GPSIDEDPCGEN | \
+	MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+	| MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
+#endif //_SOC_PANTHERLAKE_GPIO_H_
diff --git a/src/soc/intel/pantherlake/include/soc/gpio_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_defs.h
new file mode 100644
index 0000000000..e9fdc46a2c
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/gpio_defs.h
@@ -0,0 +1,277 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_GPIO_DEFS_H_
+#define _SOC_PANTHERLAKE_GPIO_DEFS_H_
+
+#include <soc/gpio_soc_defs.h>
+
+#define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
+
+#define NUM_GPIO_COMx_GPI_REGS(n)	\
+		(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM0_GRP_PADS)
+#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM1_GRP_PADS)
+#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM3_GRP_PADS)
+#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM4_GRP_PADS)
+#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_COM5_GRP_PADS)
+
+#define NUM_GPI_STATUS_REGS	\
+		((NUM_GPIO_COM0_GPI_REGS) +\
+		(NUM_GPIO_COM1_GPI_REGS) +\
+		(NUM_GPIO_COM3_GPI_REGS) +\
+		(NUM_GPIO_COM4_GPI_REGS) +\
+		(NUM_GPIO_COM5_GPI_REGS))
+
+/*
+ * IOxAPIC IRQs for the GPIOs
+ */
+
+/* Group V */
+#define GPP_V00_IRQ	0x18
+#define GPP_V01_IRQ	0x19
+#define GPP_V02_IRQ	0x1A
+#define GPP_V03_IRQ	0x1B
+#define GPP_V04_IRQ	0x1C
+#define GPP_V05_IRQ	0x1D
+#define GPP_V06_IRQ	0x1E
+#define GPP_V07_IRQ	0x1F
+#define GPP_V08_IRQ	0x20
+#define GPP_V09_IRQ	0x21
+#define GPP_V10_IRQ	0x22
+#define GPP_V11_IRQ	0x23
+#define GPP_V12_IRQ	0x24
+#define GPP_V13_IRQ	0x25
+#define GPP_V14_IRQ	0x26
+#define GPP_V15_IRQ	0x27
+#define GPP_V16_IRQ	0x28
+#define GPP_V17_IRQ	0x29
+
+/* Group C */
+#define GPP_C00_IRQ	0x2A
+#define GPP_C01_IRQ	0x2B
+#define GPP_C02_IRQ	0x2C
+#define GPP_C03_IRQ	0x2D
+#define GPP_C04_IRQ	0x2E
+#define GPP_C05_IRQ	0x2F
+#define GPP_C06_IRQ	0x30
+#define GPP_C07_IRQ	0x31
+#define GPP_C08_IRQ	0x32
+#define GPP_C09_IRQ	0x33
+#define GPP_C10_IRQ	0x34
+#define GPP_C11_IRQ	0x35
+#define GPP_C12_IRQ	0x36
+#define GPP_C13_IRQ	0x37
+#define GPP_C14_IRQ	0x38
+#define GPP_C15_IRQ	0x39
+#define GPP_C16_IRQ	0x3A
+#define GPP_C17_IRQ	0x3B
+#define GPP_C18_IRQ	0x3C
+#define GPP_C19_IRQ	0x3D
+#define GPP_C20_IRQ	0x3E
+#define GPP_C21_IRQ	0x3F
+#define GPP_C22_IRQ	0x40
+#define GPP_C23_IRQ	0x41
+
+/* Group F */
+#define GPP_F00_IRQ	0x42
+#define GPP_F01_IRQ	0x43
+#define GPP_F02_IRQ	0x44
+#define GPP_F03_IRQ	0x45
+#define GPP_F04_IRQ	0x46
+#define GPP_F05_IRQ	0x47
+#define GPP_F06_IRQ	0x48
+#define GPP_F07_IRQ	0x49
+#define GPP_F08_IRQ	0x4A
+#define GPP_F09_IRQ	0x4B
+#define GPP_F10_IRQ	0x4C
+#define GPP_F11_IRQ	0x4D
+#define GPP_F12_IRQ	0x4E
+#define GPP_F13_IRQ	0x4F
+#define GPP_F14_IRQ	0x50
+#define GPP_F15_IRQ	0x51
+#define GPP_F16_IRQ	0x52
+#define GPP_F17_IRQ	0x53
+#define GPP_F18_IRQ	0x54
+#define GPP_F19_IRQ	0x55
+#define GPP_F20_IRQ	0x56
+#define GPP_F21_IRQ	0x57
+#define GPP_F22_IRQ	0x58
+#define GPP_F23_IRQ	0x59
+
+/* Group E */
+#define GPP_E00_IRQ	0x5A
+#define GPP_E01_IRQ	0x5B
+#define GPP_E02_IRQ	0x5C
+#define GPP_E03_IRQ	0x5D
+#define GPP_E04_IRQ	0x5E
+#define GPP_E05_IRQ	0x5F
+#define GPP_E06_IRQ	0x60
+#define GPP_E07_IRQ	0x61
+#define GPP_E08_IRQ	0x62
+#define GPP_E09_IRQ	0x63
+#define GPP_E10_IRQ	0x64
+#define GPP_E11_IRQ	0x65
+#define GPP_E12_IRQ	0x66
+#define GPP_E13_IRQ	0x67
+#define GPP_E14_IRQ	0x68
+#define GPP_E15_IRQ	0x69
+#define GPP_E16_IRQ	0x6A
+#define GPP_E17_IRQ	0x6B
+#define GPP_E18_IRQ	0x6C
+#define GPP_E19_IRQ	0x6D
+#define GPP_E20_IRQ	0x6E
+#define GPP_E21_IRQ	0x6F
+#define GPP_E22_IRQ	0x70
+
+/* Group H */
+#define GPP_H00_IRQ	0x23
+#define GPP_H01_IRQ	0x24
+#define GPP_H02_IRQ	0x25
+#define GPP_H03_IRQ	0x26
+#define GPP_H04_IRQ	0x27
+#define GPP_H05_IRQ	0x28
+#define GPP_H06_IRQ	0x29
+#define GPP_H07_IRQ	0x2A
+#define GPP_H08_IRQ	0x2B
+#define GPP_H09_IRQ	0x2C
+#define GPP_H10_IRQ	0x2D
+#define GPP_H11_IRQ	0x2E
+#define GPP_H12_IRQ	0x2F
+#define GPP_H13_IRQ	0x30
+#define GPP_H14_IRQ	0x31
+#define GPP_H15_IRQ	0x32
+#define GPP_H16_IRQ	0x33
+#define GPP_H17_IRQ	0x34
+#define GPP_H18_IRQ	0x35
+#define GPP_H19_IRQ	0x36
+#define GPP_H20_IRQ	0x37
+#define GPP_H21_IRQ	0x38
+#define GPP_H22_IRQ	0x39
+#define GPP_H23_IRQ	0x3A
+#define GPP_H24_IRQ	0x3B
+
+/* Group A */
+#define GPP_A00_IRQ	0x71
+#define GPP_A01_IRQ	0x72
+#define GPP_A02_IRQ	0x73
+#define GPP_A03_IRQ	0x74
+#define GPP_A04_IRQ	0x75
+#define GPP_A05_IRQ	0x76
+#define GPP_A06_IRQ	0x77
+#define GPP_A07_IRQ	0x18
+#define GPP_A08_IRQ	0x19
+#define GPP_A09_IRQ	0x1A
+#define GPP_A10_IRQ	0x1B
+#define GPP_A11_IRQ	0x1C
+#define GPP_A12_IRQ	0x1D
+#define GPP_A13_IRQ	0x1E
+#define GPP_A14_IRQ	0x1F
+#define GPP_A15_IRQ	0x20
+#define GPP_A16_IRQ	0x21
+#define GPP_A17_IRQ	0x22
+
+/* Group B */
+#define GPP_B00_IRQ	0x42
+#define GPP_B01_IRQ	0x43
+#define GPP_B02_IRQ	0x44
+#define GPP_B03_IRQ	0x45
+#define GPP_B04_IRQ	0x46
+#define GPP_B05_IRQ	0x47
+#define GPP_B06_IRQ	0x48
+#define GPP_B07_IRQ	0x49
+#define GPP_B08_IRQ	0x4A
+#define GPP_B09_IRQ	0x4B
+#define GPP_B10_IRQ	0x4C
+#define GPP_B11_IRQ	0x4D
+#define GPP_B12_IRQ	0x4E
+#define GPP_B13_IRQ	0x4F
+#define GPP_B14_IRQ	0x50
+#define GPP_B15_IRQ	0x51
+#define GPP_B16_IRQ	0x52
+#define GPP_B17_IRQ	0x53
+#define GPP_B18_IRQ	0x54
+#define GPP_B19_IRQ	0x55
+#define GPP_B20_IRQ	0x56
+#define GPP_B21_IRQ	0x57
+#define GPP_B22_IRQ	0x58
+#define GPP_B23_IRQ	0x59
+#define GPP_B24_IRQ	0x5A
+#define GPP_B25_IRQ	0x5B
+
+/* Group D */
+#define GPP_D00_IRQ	0x5C
+#define GPP_D01_IRQ	0x5D
+#define GPP_D02_IRQ	0x5E
+#define GPP_D03_IRQ	0x5F
+#define GPP_D04_IRQ	0x60
+#define GPP_D05_IRQ	0x61
+#define GPP_D06_IRQ	0x62
+#define GPP_D07_IRQ	0x63
+#define GPP_D08_IRQ	0x64
+#define GPP_D09_IRQ	0x65
+#define GPP_D10_IRQ	0x66
+#define GPP_D11_IRQ	0x67
+#define GPP_D12_IRQ	0x68
+#define GPP_D13_IRQ	0x69
+#define GPP_D14_IRQ	0x6A
+#define GPP_D15_IRQ	0x6B
+#define GPP_D16_IRQ	0x6C
+#define GPP_D17_IRQ	0x6D
+#define GPP_D18_IRQ	0x6E
+#define GPP_D19_IRQ	0x6F
+#define GPP_D20_IRQ	0x70
+#define GPP_D21_IRQ	0x71
+#define GPP_D22_IRQ	0x72
+#define GPP_D23_IRQ	0x73
+#define GPP_D24_IRQ	0x74
+#define GPP_D25_IRQ	0x75
+
+/* Group S */
+#define GPP_S00_IRQ	0x19
+#define GPP_S01_IRQ	0x1A
+#define GPP_S02_IRQ	0x1B
+#define GPP_S03_IRQ	0x1C
+#define GPP_S04_IRQ	0x1D
+#define GPP_S05_IRQ	0x1E
+#define GPP_S06_IRQ	0x1F
+#define GPP_S07_IRQ	0x20
+
+/* Register defines. */
+#define GPIO_MISCCFG		0x10
+#define GPE_DW_SHIFT		8
+#define GPE_DW_MASK		0xfff00
+#define PAD_OWN_REG_0		0x130
+#define PAD_CFG_LOCK_REG_0	0x290
+#define HOSTSW_OWN_REG_0	0x2c0
+#define GPI_INT_STS_0		0x300
+#define GPI_INT_EN_0		0x310
+#define GPI_GPE_STS_0		0x330
+#define GPI_GPE_EN_0		0x350
+#define GPI_SMI_STS_0		0x370
+#define GPI_SMI_EN_0		0x390
+#define GPI_NMI_STS_0		0x3b0
+#define GPI_NMI_EN_0		0x3d0
+#define PAD_CFG_BASE		0x800
+#define GPP_V_START_OFFSET		0x800
+#define GPP_C_START_OFFSET		0x980
+#define GPP_F_START_OFFSET		0x800
+/*
+ * NOTE: GPP_E00 is not a connected PAD in PTL. However, for GPIO ASL file, the
+ * GPP_E00 offset 0x9a0 should be used for GPP_E group as the starting address
+ * and the total number of GPP_E group PAD is 25, E00-E22 + two internal only
+ * PADs at the end as defined in SOC gpio_soc_defs.h. GPP_E00 should be treated
+ * it as other internal used only PADs and does not meant to be used.
+ * ref doc: Panther Lake H GPIO Implementation Summary (#817954)
+ */
+#define GPP_E_START_OFFSET		0x9a0
+#define GPP_CPUJTAG_START_OFFSET	0x800
+#define GPP_H_START_OFFSET		0x8f0
+#define GPP_A_START_OFFSET		0xab0
+#define GPP_VGPIO3_START_OFFSET		0xc70
+#define GPP_S_START_OFFSET		0x800
+#define GPP_B_START_OFFSET		0x800
+#define GPP_D_START_OFFSET		0x9b0
+#define GPP_VGPIO_START_OFFSET		0xb60
+
+#endif //_SOC_PANTHERLAKE_GPIO_DEFS_H_
diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
new file mode 100644
index 0000000000..0937d1e81f
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
@@ -0,0 +1,572 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_GPIO_SOC_DEFS_H_
+#define _SOC_PANTHERLAKE_GPIO_SOC_DEFS_H_
+
+#define INC(x) ((x) + 1)
+
+/*
+ * Most of the fixed numbers and macros are based on the GPP groups.
+ * The GPIO groups are accessed through register blocks called
+ * communities.
+ */
+/* GPIO COMM 0 */
+#define GPP_V		0x0
+#define GPP_C		0x1
+/* GPIO COMM 1 */
+#define GPP_F		0x2
+#define GPP_E		0x3
+/* GPIO COMM 3 */
+#define GPP_A		0x4
+#define GPP_H		0x5
+/* GPIO COMM 4 */
+#define GPP_S		0x9
+/* GPIO COMM 5 */
+#define GPP_B		0x7
+#define GPP_D		0x8
+#define GPP_VGPIO	0x6
+
+/* for ACPI _UID */
+#define GPP_COMM0_ID 0
+#define GPP_COMM1_ID 1
+#define GPP_COMM3_ID 3
+#define GPP_COMM4_ID 4
+#define GPP_COMM5_ID 5
+
+#define GPP_V_NAME		"GPP_V"
+#define GPP_C_NAME		"GPP_C"
+#define GPP_F_NAME		"GPP_F"
+#define GPP_E_NAME		"GPP_E"
+#define GPP_CPUJTAG_NAME	"GPUJTAG"
+#define GPP_H_NAME		"GPP_H"
+#define GPP_A_NAME		"GPP_A"
+#define GPP_VGPIO3_NAME		"vGPIO_3"
+#define GPP_S_NAME		"GPP_S"
+#define GPP_B_NAME		"GPP_B"
+#define GPP_D_NAME		"GPP_D"
+#define GPP_VGPIO_NAME		"vGPIO"
+
+#define GPIO_MAX_NUM_PER_GROUP	28
+
+#define COMM_0		0
+#define COMM_1		INC(COMM_0)
+#define COMM_3		INC(COMM_1)
+#define COMM_4		INC(COMM_3)
+#define COMM_5		INC(COMM_4)
+
+/*
+ * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
+ */
+/*
+ * +----------------------------+
+ * | Community 0                |
+ * +----------------------------+
+ */
+
+/*
+ * +----------------------------+
+ * |        Group V             |
+ * +------------------+---------+
+ * |                  | PTL-U/H |
+ * +------------------+---------+
+ * | Pad Start Number |    0    |
+ * +------------------+---------+
+ * | Pad End Number   |    23   |
+ * +------------------+---------+
+ */
+#define GPP_V00			0
+#define GPP_V01			INC(GPP_V00)
+#define GPP_V02			INC(GPP_V01)
+#define GPP_V03			INC(GPP_V02)
+#define GPP_V04			INC(GPP_V03)
+#define GPP_V05			INC(GPP_V04)
+#define GPP_V06			INC(GPP_V05)
+#define GPP_V07			INC(GPP_V06)
+#define GPP_V08			INC(GPP_V07)
+#define GPP_V09			INC(GPP_V08)
+#define GPP_V10			INC(GPP_V09)
+#define GPP_V11			INC(GPP_V10)
+#define GPP_V12			INC(GPP_V11)
+#define GPP_V13			INC(GPP_V12)
+#define GPP_V14			INC(GPP_V13)
+#define GPP_V15			INC(GPP_V14)
+#define GPP_V16			INC(GPP_V15)
+#define GPP_V17			INC(GPP_V16)
+
+#define GPP_PWROK		INC(GPP_V17)
+#define GPP_RESET_B		INC(GPP_PWROK)
+#define GPP_BKLTEN		INC(GPP_RESET_B)
+#define GPP_BKLTCTL		INC(GPP_BKLTEN)
+#define GPP_VDDEN		INC(GPP_BKLTCTL)
+#define GPP_RST_B		INC(GPP_VDDEN)
+
+#define NUM_GRP_V_PADS		(GPP_RST_B - GPP_V00 + 1)
+#define NUM_GPP_V_PADS		(GPP_V17 - GPP_V00 + 1)
+
+/*
+ * +----------------------------+
+ * |        Group C             |
+ * +------------------+---------+
+ * |                  | PTL-UH/H|
+ * +------------------+---------+
+ * | Pad Start Number |    24   |
+ * +------------------+---------+
+ * | Pad End Number   |    47   |
+ * +------------------+---------+
+ */
+#define GPP_C00			INC(GPP_RST_B)
+#define GPP_C01			INC(GPP_C00)
+#define GPP_C02			INC(GPP_C01)
+#define GPP_C03			INC(GPP_C02)
+#define GPP_C04			INC(GPP_C03)
+#define GPP_C05			INC(GPP_C04)
+#define GPP_C06			INC(GPP_C05)
+#define GPP_C07			INC(GPP_C06)
+#define GPP_C08			INC(GPP_C07)
+#define GPP_C09			INC(GPP_C08)
+#define GPP_C10			INC(GPP_C09)
+#define GPP_C11			INC(GPP_C10)
+#define GPP_C12			INC(GPP_C11)
+#define GPP_C13			INC(GPP_C12)
+#define GPP_C14			INC(GPP_C13)
+#define GPP_C15			INC(GPP_C14)
+#define GPP_C16			INC(GPP_C15)
+#define GPP_C17			INC(GPP_C16)
+#define GPP_C18			INC(GPP_C17)
+#define GPP_C19			INC(GPP_C18)
+#define GPP_C20			INC(GPP_C19)
+#define GPP_C21			INC(GPP_C20)
+#define GPP_C22			INC(GPP_C21)
+#define GPP_C23			INC(GPP_C22)
+
+#define NUM_GRP_C_PADS		(GPP_C23 - GPP_C00 + 1)
+#define NUM_GPP_C_PADS		(GPP_C23 - GPP_C00 + 1)
+
+#define COM0_GRP_PAD_START	GPP_V00
+#define COM0_GRP_PAD_END	GPP_C23
+#define NUM_COM0_GRP_PADS	(GPP_C23 - GPP_V00 + 1)
+#define NUM_COM0_GPP_PADS	(NUM_GPP_V_PADS + NUM_GPP_C_PADS)
+#define NUM_COM0_GROUPS		2
+
+/*
+ * +----------------------------+
+ * | Community 1                |
+ * +----------------------------+
+ */
+
+/*
+ * +----------------------------+
+ * |        Group F             |
+ * +------------------+---------+
+ * |                  | PTL-UH/H|
+ * +------------------+---------+
+ * | Pad Start Number |    48   |
+ * +------------------+---------+
+ * | Pad End Number   |    73   |
+ * +------------------+---------+
+ */
+#define GPP_F00			INC(GPP_C23)
+#define GPP_F01			INC(GPP_F00)
+#define GPP_F02			INC(GPP_F01)
+#define GPP_F03			INC(GPP_F02)
+#define GPP_F04			INC(GPP_F03)
+#define GPP_F05			INC(GPP_F04)
+#define GPP_F06			INC(GPP_F05)
+#define GPP_F07			INC(GPP_F06)
+#define GPP_F08			INC(GPP_F07)
+#define GPP_F09			INC(GPP_F08)
+#define GPP_F10			INC(GPP_F09)
+#define GPP_F11			INC(GPP_F10)
+#define GPP_F12			INC(GPP_F11)
+#define GPP_F13			INC(GPP_F12)
+#define GPP_F14			INC(GPP_F13)
+#define GPP_F15			INC(GPP_F14)
+#define GPP_F16			INC(GPP_F15)
+#define GPP_F17			INC(GPP_F16)
+#define GPP_F18			INC(GPP_F17)
+#define GPP_F19			INC(GPP_F18)
+#define GPP_F20			INC(GPP_F19)
+#define GPP_F21			INC(GPP_F20)
+#define GPP_F22			INC(GPP_F21)
+#define GPP_F23			INC(GPP_F22)
+#define GPP_THC1_GSPI1_CLK_LPBK	INC(GPP_F23)
+#define GPP_GSPI0_CLK_LOOPBK	INC(GPP_THC1_GSPI1_CLK_LPBK)
+
+#define NUM_GRP_F_PADS		(GPP_GSPI0_CLK_LOOPBK - GPP_F00 + 1)
+#define NUM_GPP_F_PADS		(GPP_F23 - GPP_F00 + 1)
+
+/*
+ * +----------------------------+
+ * |        Group E             |
+ * +------------------+---------+
+ * |                  | PTL-UH/H|
+ * +------------------+---------+
+ * | Pad Start Number |    74   |
+ * +------------------+---------+
+ * | Pad End Number   |    98   |
+ * +------------------+---------+
+ *
+ * NOTE: GPP_E00 is not a connected PAD in PTL and should be treated
+ * as other internal used only PADs. It does not meant to be used.
+ * ref doc: Panther Lake H GPIO Implementation Summary (#817954)
+ */
+#define GPP_E00			INC(GPP_GSPI0_CLK_LOOPBK)
+#define GPP_E01			INC(GPP_E00)
+#define GPP_E02			INC(GPP_E01)
+#define GPP_E03			INC(GPP_E02)
+#define GPP_E04			INC(GPP_E03)
+#define GPP_E05			INC(GPP_E04)
+#define GPP_E06			INC(GPP_E05)
+#define GPP_E07			INC(GPP_E06)
+#define GPP_E08			INC(GPP_E07)
+#define GPP_E09			INC(GPP_E08)
+#define GPP_E10			INC(GPP_E09)
+#define GPP_E11			INC(GPP_E10)
+#define GPP_E12			INC(GPP_E11)
+#define GPP_E13			INC(GPP_E12)
+#define GPP_E14			INC(GPP_E13)
+#define GPP_E15			INC(GPP_E14)
+#define GPP_E16			INC(GPP_E15)
+#define GPP_E17			INC(GPP_E16)
+#define GPP_E18			INC(GPP_E17)
+#define GPP_E19			INC(GPP_E18)
+#define GPP_E20			INC(GPP_E19)
+#define GPP_E21			INC(GPP_E20)
+#define GPP_E22			INC(GPP_E21)
+#define GPP_BOOTHALT_B		INC(GPP_E22)
+#define GPP_THC0_GSPI_CLK_LPBK	INC(GPP_BOOTHALT_B)
+
+#define NUM_GRP_E_PADS		(GPP_THC0_GSPI_CLK_LPBK - GPP_E00 + 1)
+#define NUM_GPP_E_PADS		(GPP_E22 - GPP_E00 + 1)
+
+#define COM1_GRP_PAD_START	GPP_F00
+#define COM1_GRP_PAD_END	GPP_THC0_GSPI_CLK_LPBK
+#define NUM_COM1_GRP_PADS	(GPP_THC0_GSPI_CLK_LPBK - GPP_F00 + 1)
+#define NUM_COM1_GPP_PADS	(NUM_GPP_F_PADS + NUM_GPP_E_PADS)
+#define NUM_COM1_GROUPS		2
+
+/*
+ * +----------------------------+
+ * | Community 3                |
+ * +----------------------------+
+ */
+
+/*
+ * +----------------------------+
+ * |        Group CPUJTAG       |
+ * +------------------+---------+
+ * |                  | PTL-UH/H|
+ * +------------------+---------+
+ * | Pad Start Number |    99   |
+ * +------------------+---------+
+ * | Pad End Number   |    113  |
+ * +------------------+---------+
+ */
+
+#define GPP_EPD_ON		INC(GPP_THC0_GSPI_CLK_LPBK)
+#define GPP_VDD2_PWRGD		INC(GPP_EPD_ON)
+
+#define GPP_JTAG_MBPB0		INC(GPP_VDD2_PWRGD)
+#define GPP_JTAG_MBPB1		INC(GPP_JTAG_MBPB0)
+#define GPP_JTAG_MBPB2		INC(GPP_JTAG_MBPB1)
+#define GPP_JTAG_MBPB3		INC(GPP_JTAG_MBPB2)
+#define GPP_JTAG_TD0		INC(GPP_JTAG_MBPB3)
+#define GPP_PRDY_B		INC(GPP_JTAG_TD0)
+#define GPP_PREQ_B		INC(GPP_PRDY_B)
+#define GPP_JTAG_TDI		INC(GPP_PREQ_B)
+#define GPP_JTAG_TMS		INC(GPP_JTAG_TDI)
+#define GPP_JTAG_TCK		INC(GPP_JTAG_TMS)
+#define GPP_DBG_PMODE		INC(GPP_JTAG_TCK)
+#define GPP_JTAG_TRST_B		INC(GPP_DBG_PMODE)
+#define GPP_DDSP_HPDALV		INC(GPP_JTAG_TRST_B)
+
+#define NUM_GRP_CPUJTAG_PADS	(GPP_DDSP_HPDALV - GPP_EPD_ON + 1)
+
+/*
+ * +----------------------------+
+ * |        Group H             |
+ * +------------------+---------+
+ * |                  | PTL-UH/H|
+ * +------------------+---------+
+ * | Pad Start Number |    114  |
+ * +------------------+---------+
+ * | Pad End Number   |    141  |
+ * +------------------+---------+
+ */
+#define GPP_H00			INC(GPP_DDSP_HPDALV)
+#define GPP_H01			INC(GPP_H00)
+#define GPP_H02			INC(GPP_H01)
+#define GPP_H03			INC(GPP_H02)
+#define GPP_H04			INC(GPP_H03)
+#define GPP_H05			INC(GPP_H04)
+#define GPP_H06			INC(GPP_H05)
+#define GPP_H07			INC(GPP_H06)
+#define GPP_H08			INC(GPP_H07)
+#define GPP_H09			INC(GPP_H08)
+#define GPP_H10			INC(GPP_H09)
+#define GPP_H11			INC(GPP_H10)
+#define GPP_H12			INC(GPP_H11)
+#define GPP_H13			INC(GPP_H12)
+#define GPP_H14			INC(GPP_H13)
+#define GPP_H15			INC(GPP_H14)
+#define GPP_H16			INC(GPP_H15)
+#define GPP_H17			INC(GPP_H16)
+#define GPP_H18			INC(GPP_H17)
+#define GPP_H19			INC(GPP_H18)
+#define GPP_H20			INC(GPP_H19)
+#define GPP_H21			INC(GPP_H20)
+#define GPP_H22			INC(GPP_H21)
+#define GPP_H23			INC(GPP_H22)
+#define GPP_H24			INC(GPP_H23)
+#define GPP_LPI3C1_CLK_LPBK	INC(GPP_H24)
+#define GPP_LPI3C0_CLK_LPBK	INC(GPP_LPI3C1_CLK_LPBK)
+#define GPP_ISHI3C1_CLK_LPBK	INC(GPP_LPI3C0_CLK_LPBK)
+
+#define NUM_GRP_H_PADS		(GPP_ISHI3C1_CLK_LPBK - GPP_H00 + 1)
+#define NUM_GPP_H_PADS		(GPP_H24 - GPP_H00 + 1)
+
+/*
+ * +----------------------------+
+ * |        Group A             |
+ * +------------------+---------+
+ * |                  | PTL-UH/H|
+ * +------------------+---------+
+ * | Pad Start Number |    142  |
+ * +------------------+---------+
+ * | Pad End Number   |    169  |
+ * +------------------+---------+
+ */
+#define GPP_A00			INC(GPP_ISHI3C1_CLK_LPBK)
+#define GPP_A01			INC(GPP_A00)
+#define GPP_A02			INC(GPP_A01)
+#define GPP_A03			INC(GPP_A02)
+#define GPP_A04			INC(GPP_A03)
+#define GPP_A05			INC(GPP_A04)
+#define GPP_A06			INC(GPP_A05)
+#define GPP_A07			INC(GPP_A06)
+#define GPP_A08			INC(GPP_A07)
+#define GPP_A09			INC(GPP_A08)
+#define GPP_A10			INC(GPP_A09)
+#define GPP_A11			INC(GPP_A10)
+#define GPP_A12			INC(GPP_A11)
+#define GPP_A13			INC(GPP_A12)
+#define GPP_A14			INC(GPP_A13)
+#define GPP_A15			INC(GPP_A14)
+#define GPP_A16			INC(GPP_A15)
+#define GPP_A17			INC(GPP_A16)
+/* SPI0 PADs */
+#define GPP_SPI0_IO_2		INC(GPP_A17)
+#define GPP_SPI0_IO_3		INC(GPP_SPI0_IO_2)
+#define GPP_SPI0_MOSI_IO_0	INC(GPP_SPI0_IO_3)
+#define GPP_SPI0_MOSI_IO_1	INC(GPP_SPI0_MOSI_IO_0)
+#define GPP_SPI0_TPM_CS_B	INC(GPP_SPI0_MOSI_IO_1)
+#define GPP_SPI0_FLASH_0_CS_B	INC(GPP_SPI0_TPM_CS_B)
+#define GPP_SPI0_FLASH_1_CS_B	INC(GPP_SPI0_FLASH_0_CS_B)
+#define GPP_SPI0_CLK		INC(GPP_SPI0_FLASH_1_CS_B)
+#define GPP_ESPI_CLK_LPBK	INC(GPP_SPI0_CLK)
+#define GPP_SPI0_CLK_LOOPBK	INC(GPP_ESPI_CLK_LPBK)
+
+#define NUM_GRP_A_PADS		(GPP_SPI0_CLK_LOOPBK - GPP_A00 + 1)
+#define NUM_GPP_A_PADS		(GPP_A17 - GPP_A00 + 1)
+
+/*
+ * +----------------------------+
+ * |        Group vGPIO3        |
+ * +------------------+---------+
+ * |                  | PTL-UH/H|
+ * +------------------+---------+
+ * | Pad Start Number |    170  |
+ * +------------------+---------+
+ * | Pad End Number   |    183  |
+ * +------------------+---------+
+ */
+#define GPP_VGPIO3_USB0		INC(GPP_SPI0_CLK_LOOPBK)
+#define GPP_VGPIO3_USB1		INC(GPP_VGPIO3_USB0)
+#define GPP_VGPIO3_USB2		INC(GPP_VGPIO3_USB1)
+#define GPP_VGPIO3_USB3		INC(GPP_VGPIO3_USB2)
+#define GPP_VGPIO3_USB4		INC(GPP_VGPIO3_USB3)
+#define GPP_VGPIO3_USB5		INC(GPP_VGPIO3_USB4)
+#define GPP_VGPIO3_USB6		INC(GPP_VGPIO3_USB5)
+#define GPP_VGPIO3_USB7		INC(GPP_VGPIO3_USB6)
+#define GPP_VGPIO3_TS0		INC(GPP_VGPIO3_USB7)
+#define GPP_VGPIO3_TS1		INC(GPP_VGPIO3_TS0)
+#define GPP_VGPIO3_THC0		INC(GPP_VGPIO3_TS1)
+#define GPP_VGPIO3_THC1		INC(GPP_VGPIO3_THC0)
+#define GPP_VGPIO3_THC2		INC(GPP_VGPIO3_THC1)
+#define GPP_VGPIO3_THC3		INC(GPP_VGPIO3_THC2)
+
+#define NUM_GRP_VGPIO3_PADS	(GPP_VGPIO3_THC3 - GPP_VGPIO3_USB0 + 1)
+
+#define COM3_GRP_PAD_START	GPP_EPD_ON
+#define COM3_GRP_PAD_END	GPP_VGPIO3_THC3
+#define NUM_COM3_GRP_PADS	(GPP_VGPIO3_THC3 - GPP_EPD_ON + 1)
+#define NUM_COM3_GPP_PADS	(NUM_GPP_H_PADS + NUM_GPP_A_PADS)
+#define NUM_COM3_GROUPS		4
+
+/*
+ * +----------------------------+
+ * | Community 4                |
+ * +----------------------------+
+ */
+
+/*
+ * +----------------------------+
+ * |        Group S             |
+ * +------------------+---------+
+ * |                  | PTL-UH/H|
+ * +------------------+---------+
+ * | Pad Start Number |    184  |
+ * +------------------+---------+
+ * | Pad End Number   |    191  |
+ * +------------------+---------+
+ */
+#define GPP_S00			INC(GPP_VGPIO3_THC3)
+#define GPP_S01			INC(GPP_S00)
+#define GPP_S02			INC(GPP_S01)
+#define GPP_S03			INC(GPP_S02)
+#define GPP_S04			INC(GPP_S03)
+#define GPP_S05			INC(GPP_S04)
+#define GPP_S06			INC(GPP_S05)
+#define GPP_S07			INC(GPP_S06)
+
+#define NUM_GRP_S_PADS		(GPP_S07 - GPP_S00 + 1)
+#define NUM_GPP_S_PADS		(GPP_S07 - GPP_S00 + 1)
+
+#define COM4_GRP_PAD_START	GPP_S00
+#define COM4_GRP_PAD_END	GPP_S07
+#define NUM_COM4_GRP_PADS	(GPP_S07 - GPP_S00 + 1)
+#define NUM_COM4_GPP_PADS	(GPP_S07 - GPP_S00 + 1)
+#define NUM_COM4_GROUPS		1
+
+/*
+ * +----------------------------+
+ * | Community 5                |
+ * +----------------------------+
+ */
+
+/*
+ * +----------------------------+
+ * |        Group B             |
+ * +------------------+---------+
+ * |                  | PTL-UH/H|
+ * +------------------+---------+
+ * | Pad Start Number |    192  |
+ * +------------------+---------+
+ * | Pad End Number   |    218  |
+ * +------------------+---------+
+ */
+#define GPP_B00			INC(GPP_S07)
+#define GPP_B01			INC(GPP_B00)
+#define GPP_B02			INC(GPP_B01)
+#define GPP_B03			INC(GPP_B02)
+#define GPP_B04			INC(GPP_B03)
+#define GPP_B05			INC(GPP_B04)
+#define GPP_B06			INC(GPP_B05)
+#define GPP_B07			INC(GPP_B06)
+#define GPP_B08			INC(GPP_B07)
+#define GPP_B09			INC(GPP_B08)
+#define GPP_B10			INC(GPP_B09)
+#define GPP_B11			INC(GPP_B10)
+#define GPP_B12			INC(GPP_B11)
+#define GPP_B13			INC(GPP_B12)
+#define GPP_B14			INC(GPP_B13)
+#define GPP_B15			INC(GPP_B14)
+#define GPP_B16			INC(GPP_B15)
+#define GPP_B17			INC(GPP_B16)
+#define GPP_B18			INC(GPP_B17)
+#define GPP_B19			INC(GPP_B18)
+#define GPP_B20			INC(GPP_B19)
+#define GPP_B21			INC(GPP_B20)
+#define GPP_B22			INC(GPP_B21)
+#define GPP_B23			INC(GPP_B22)
+#define GPP_B24			INC(GPP_B23)
+#define GPP_B25			INC(GPP_B24)
+#define GPP_ISHI3C0_CLK_LPBK	INC(GPP_B25)
+
+#define NUM_GRP_B_PADS		(GPP_ISHI3C0_CLK_LPBK - GPP_B00 + 1)
+#define NUM_GPP_B_PADS		(GPP_B25 - GPP_B00 + 1)
+
+/*
+ * +----------------------------+
+ * |        Group D             |
+ * +------------------+---------+
+ * |                  | PTL-UH/H|
+ * +------------------+---------+
+ * | Pad Start Number |    219  |
+ * +------------------+---------+
+ * | Pad End Number   |    245  |
+ * +------------------+---------+
+ */
+#define GPP_D00			INC(GPP_ISHI3C0_CLK_LPBK)
+#define GPP_D01			INC(GPP_D00)
+#define GPP_D02			INC(GPP_D01)
+#define GPP_D03			INC(GPP_D02)
+#define GPP_D04			INC(GPP_D03)
+#define GPP_D05			INC(GPP_D04)
+#define GPP_D06			INC(GPP_D05)
+#define GPP_D07			INC(GPP_D06)
+#define GPP_D08			INC(GPP_D07)
+#define GPP_D09			INC(GPP_D08)
+#define GPP_D10			INC(GPP_D09)
+#define GPP_D11			INC(GPP_D10)
+#define GPP_D12			INC(GPP_D11)
+#define GPP_D13			INC(GPP_D12)
+#define GPP_D14			INC(GPP_D13)
+#define GPP_D15			INC(GPP_D14)
+#define GPP_D16			INC(GPP_D15)
+#define GPP_D17			INC(GPP_D16)
+#define GPP_D18			INC(GPP_D17)
+#define GPP_D19			INC(GPP_D18)
+#define GPP_D20			INC(GPP_D19)
+#define GPP_D21			INC(GPP_D20)
+#define GPP_D22			INC(GPP_D21)
+#define GPP_D23			INC(GPP_D22)
+#define GPP_D24			INC(GPP_D23)
+#define GPP_D25			INC(GPP_D24)
+#define GPP_ISDI3C1_CLK_LPBK	INC(GPP_D25)
+
+#define NUM_GRP_D_PADS		(GPP_ISDI3C1_CLK_LPBK - GPP_D00 + 1)
+#define NUM_GPP_D_PADS		(GPP_D25 - GPP_D00 + 1)
+
+/*
+ * +----------------------------+
+ * |        Group vGPIO         |
+ * +------------------+---------+
+ * |                  | PTL-UH/H|
+ * +------------------+---------+
+ * | Pad Start Number |    246  |
+ * +------------------+---------+
+ * | Pad End Number   |    263  |
+ * +------------------+---------+
+ */
+#define GPP_VGPIO0		INC(GPP_ISDI3C1_CLK_LPBK)
+#define GPP_VGPIO5		INC(GPP_VGPIO0)
+#define GPP_VGPIO30		INC(GPP_VGPIO5)
+#define GPP_VGPIO31		INC(GPP_VGPIO30)
+#define GPP_VGPIO32		INC(GPP_VGPIO31)
+#define GPP_VGPIO33		INC(GPP_VGPIO32)
+#define GPP_VGPIO34		INC(GPP_VGPIO33)
+#define GPP_VGPIO35		INC(GPP_VGPIO34)
+#define GPP_VGPIO36		INC(GPP_VGPIO35)
+#define GPP_VGPIO37		INC(GPP_VGPIO36)
+#define GPP_VGPIO40		INC(GPP_VGPIO37)
+#define GPP_VGPIO41		INC(GPP_VGPIO40)
+#define GPP_VGPIO42		INC(GPP_VGPIO41)
+#define GPP_VGPIO43		INC(GPP_VGPIO42)
+#define GPP_VGPIO44		INC(GPP_VGPIO43)
+#define GPP_VGPIO45		INC(GPP_VGPIO44)
+#define GPP_VGPIO46		INC(GPP_VGPIO45)
+#define GPP_VGPIO47		INC(GPP_VGPIO46)
+
+#define NUM_GRP_VGPIO_PADS	(GPP_VGPIO47 - GPP_VGPIO0 + 1)
+
+#define COM5_GRP_PAD_START	GPP_B00
+#define COM5_GRP_PAD_END	GPP_VGPIO47
+#define NUM_COM5_GRP_PADS	(GPP_VGPIO47 - GPP_B00 + 1)
+#define NUM_COM5_GPP_PADS	(NUM_GPP_B_PADS + NUM_GPP_D_PADS)
+#define NUM_COM5_GROUPS		3
+
+#define TOTAL_GPIO_COMM		(COMM_5 + 1)
+#define TOTAL_PADS		(COM5_GRP_PAD_END + 1)
+
+#endif /* _SOC_PANTHERLAKE_GPIO_SOC_DEFS_H_ */