6 files changed, 24 insertions, 32 deletions
diff --git a/src/cpu/p6/earlymtrr.c b/src/cpu/p6/earlymtrr.c
index c4563ea860..707923b231 100644
--- a/src/cpu/p6/earlymtrr.c
+++ b/src/cpu/p6/earlymtrr.c
@@ -37,7 +37,7 @@ static void early_mtrr_init(void)
 	const unsigned long *msr_addr;
 	unsigned long cr0;
 
-	print_err("Disabling cache\n");
+	print_err("Disabling cache\r\n");
 	/* Just to be sure, take all the steps to disable the cache.
 	 * This may not be needed, but C3's may...
 	 * Invalidate the cache */
@@ -56,7 +56,7 @@ static void early_mtrr_init(void)
 	/* Invalidate the cache again */
 	asm volatile ("invd");
 
-	print_err("Clearing mtrr\n");
+	print_err("Clearing mtrr\r\n");
 
 	/* Inialize all of the relevant msrs to 0 */
 	msr.lo = 0;
@@ -81,7 +81,7 @@ static void early_mtrr_init(void)
 	wrmsr(0x201, msr);
 
 #if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
-	print_err("Setting XIP\n");
+	print_err("Setting XIP\r\n");
 	/* enable write through caching so we can do execute in place
 	 * on the flash rom.
 	 */
@@ -104,5 +104,5 @@ static void early_mtrr_init(void)
 	cr0 = read_cr0();
 	cr0 &= 0x9fffffff;
 	write_cr0(cr0);
-	print_err("Enabled the cache\n");
+	print_err("Enabled the cache\r\n");
 }
diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb
index ba2d0b28af..a364b8f810 100644
--- a/src/mainboard/via/epia/Config.lb
+++ b/src/mainboard/via/epia/Config.lb
@@ -50,12 +50,6 @@ object irq_tables.o
 ##
 option HAVE_OPTION_TABLE=1
 
-##
-## Clean up the motherboard id strings
-##
-option MAINBOARD_PART_NUMBER="HDAMA"
-option MAINBOARD_VENDOR="ARIMA"
-
 ###
 ### LinuxBIOS layout values
 ###
@@ -137,7 +131,7 @@ end
 
 makerule ./failover.inc
 	depends "./failover.E ./romcc"
-	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+	action "./romcc -O2 -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
 end
 
 makerule ./auto.E 
@@ -146,7 +140,7 @@ makerule ./auto.E
 end
 makerule ./auto.inc 
 	depends "./auto.E ./romcc"
-	action	"./romcc   -O ./auto.E > auto.inc"
+	action	"./romcc   -O2 -mcpu=c3 ./auto.E > auto.inc"
 end
 
 ##
diff --git a/src/mainboard/via/epia/auto.c b/src/mainboard/via/epia/auto.c
index c1a6b9b98c..fcb48a8953 100644
--- a/src/mainboard/via/epia/auto.c
+++ b/src/mainboard/via/epia/auto.c
@@ -1,5 +1,7 @@
 #define ASSEMBLY 1
 
+#define MAXIMUM_CONSOLE_LOGLEVEL 6
+#define DEFAULT_CONSOLE_LOGLEVEL 6
 
 #include <stdint.h>
 #include <device/pci_def.h>
@@ -27,8 +29,6 @@ void udelay(int usecs)
 
 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
 
-#define MAXIMUM_CONSOLE_LOGLEVEL 6
-#define DEFAULT_CONSOLE_LOGLEVEL 6
 
 #include "southbridge/via/vt8231/vt8231_early_serial.c"
 static void memreset_setup(void)
diff --git a/src/northbridge/via/vt8601/raminit.c b/src/northbridge/via/vt8601/raminit.c
index 57738e336e..5321e60f66 100644
--- a/src/northbridge/via/vt8601/raminit.c
+++ b/src/northbridge/via/vt8601/raminit.c
@@ -455,11 +455,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	//  for(i = 0; i < 8; i++)
 	base = do_module_size(0); /*, base);*/
 	pci_write_config8(north, ramregs[0], base);
-	base = do_module_size(1); /*, base);*/
-	base += pci_read_config8(north, ramregs[0]);
+	base += do_module_size(1); /*, base);*/
 	pci_write_config8(north, ramregs[1], base);
 	/* runs out of code space. */
-	for(i = 0; i < 8; i++){
+	for(i = 2; i < 8; i++){
 		pci_write_config8(north, ramregs[i], base);
 		/*
 		  pci_write_config8(north, ramregs[3], base);
diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c
index 55e833d7b5..1719fb207d 100644
--- a/src/southbridge/via/vt8231/vt8231.c
+++ b/src/southbridge/via/vt8231/vt8231.c
@@ -437,7 +437,6 @@ static void southbridge_init(struct chip *chip, enum chip_pass pass)
 		
 	case CONF_PASS_POST_PCI:
 		vt8231_init(conf);
-		printk_err("FUCK! ROUTING FIXUP!\n");
 		pci_routing_fixup();
 		
 		break;
diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c
index e419d59b63..1888176144 100644
--- a/src/southbridge/via/vt8231/vt8231_early_smbus.c
+++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c
@@ -47,8 +47,8 @@ static void enable_smbus(void)
 	c = pci_read_config8(dev, 4);
 	c |= 1;
 	pci_write_config8(dev, 4, c);
-	print_err_hex8(c);
-	print_err(" is the comm register\n");
+	print_debug_hex8(c);
+	print_debug(" is the comm register\r\n");
 	
 	print_debug("SMBus controller enabled\r\n");
 }
@@ -69,9 +69,9 @@ static int smbus_wait_until_ready(void)
 		smbus_delay();
 		c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
 		while((c & 1) == 1) {
-			print_err("c is ");
-			print_err_hex8(c);
-			print_err("\n");
+			print_debug("c is ");
+			print_debug_hex8(c);
+			print_debug("\r\n");
 			c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
 			/* nop */ 
 		}
@@ -88,9 +88,9 @@ void smbus_reset(void)
 	outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
 	
 	smbus_wait_until_ready();
-	print_err("After reset status ");
-	print_err_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
-	print_err("\n");
+	print_debug("After reset status ");
+	print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
+	print_debug("\r\n");
 }
   
 
@@ -117,21 +117,21 @@ static void smbus_print_error(unsigned char host_status_register)
 
 	print_err("smbus_error: ");
 	print_err_hex8(host_status_register);
-	print_err("\n");
+	print_err("\r\n");
 	if (host_status_register & (1 << 4)) {
-		print_err("Interrup/SMI# was Failed Bus Transaction\n");
+		print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
 	}
 	if (host_status_register & (1 << 3)) {
-		print_err("Bus Error\n");
+		print_err("Bus Error\r\n");
 	}
 	if (host_status_register & (1 << 2)) {
-		print_err("Device Error\n");
+		print_err("Device Error\r\n");
 	}
 	if (host_status_register & (1 << 1)) {
-		print_err("Interrupt/SMI# was Successful Completion\n");
+		print_err("Interrupt/SMI# was Successful Completion\r\n");
 	}
 	if (host_status_register & (1 << 0)) {
-		print_err("Host Busy\n");
+		print_err("Host Busy\r\n");
 	}
 }