diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/gaelin/gpio.c | 4 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/gaelin/overridetree.cb | 9 |
2 files changed, 11 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/gaelin/gpio.c b/src/mainboard/google/brya/variants/gaelin/gpio.c index a20e3852ae..1438975b25 100644 --- a/src/mainboard/google/brya/variants/gaelin/gpio.c +++ b/src/mainboard/google/brya/variants/gaelin/gpio.c @@ -10,7 +10,7 @@ static const struct pad_config override_gpio_table[] = { /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ - PAD_CFG_GPO(GPP_A17, 0, DEEP), + PAD_CFG_GPO(GPP_A17, 1, DEEP), /* A19 : DDSP_HPD1 ==> NC */ PAD_NC(GPP_A19, NONE), /* A20 : DDSP_HPD2 ==> NC */ @@ -62,7 +62,7 @@ static const struct pad_config override_gpio_table[] = { /* E5 : SATA_DEVSLP1 ==> USB_A1_RT_RST_ODL */ PAD_CFG_GPO(GPP_E5, 1, DEEP), /* E7 : PROC_GP1 ==> EN_MIC_PWR */ - PAD_CFG_GPO(GPP_E7, 0, DEEP), + PAD_CFG_GPO(GPP_E7, 1, DEEP), /* E14 : DDSP_HPDA ==> EDP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : RSVD_TP ==> PCH_WP_OD */ diff --git a/src/mainboard/google/brya/variants/gaelin/overridetree.cb b/src/mainboard/google/brya/variants/gaelin/overridetree.cb index dcb695fde9..57079f3d69 100644 --- a/src/mainboard/google/brya/variants/gaelin/overridetree.cb +++ b/src/mainboard/google/brya/variants/gaelin/overridetree.cb @@ -2,6 +2,7 @@ chip soc/intel/alderlake register "usb2_ports[2]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # UFCamera register "usb3_ports[2]" = "USB3_PORT_EMPTY" register "usb3_ports[3]" = "USB3_PORT_EMPTY" @@ -101,6 +102,14 @@ chip soc/intel/alderlake device ref usb2_port2 on end end chip drivers/usb/acpi + register "desc" = ""UFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A17)" + register "enable_delay_ms" = "20" + device ref usb2_port5 on end + end + chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A3 (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" |