diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 22 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/pmutil.c | 40 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/smihandler.c | 36 |
3 files changed, 46 insertions, 52 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 6b12886c07..c889453f2e 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -84,6 +84,28 @@ #define GBL_SMI_EN (1 << SMI_GBL) /* Global SMI Enable */ #define SMI_STS 0x44 +/* Bits for SMI status */ +#define PMC_OCP_SMI_STS 27 +#define SPI_SMI_STS 26 +#define SPI_SSMI_STS 25 +#define SCC2_SMI_STS 21 +#define PCIE_SMI_STS 20 +#define SCS_SMI_STS 19 +#define HSMBUS_SMI_STS 18 +#define XHCI_SMI_STS 17 +#define SMBUS_SMI_STS 16 +#define SERIRQ_SMI_STS 15 +#define PERIODIC_SMI_STS 14 +#define TCO_SMI_STS 13 +#define MC_SMI_STS 12 +#define GPIO_UNLOCK_SMI_STS 11 +#define GPIO_SMI_STS 10 +#define SWSMI_TMR_SMI_STS 6 +#define APM_SMI_STS 5 +#define SLP_SMI_STS 4 +#define LEGACY_USB_SMI_STS 3 +#define BIOS_SMI_STS 2 + #define GPE_CNTL 0x50 #define DEVACT_STS 0x4c #define TCO_STS 0x64 diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 9340ba53d2..bebc1c7178 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -55,26 +55,26 @@ static void print_num_status_bits(int num_bits, uint32_t status, static uint32_t print_smi_status(uint32_t smi_sts) { static const char * const smi_sts_bits[] = { - [2] = "BIOS", - [3] = "LEGACY USB", - [4] = "SLP_SMI", - [5] = "APM", - [6] = "SWSMI_TMR", - [10]= "GPIO_SMI", - [11]= "GPIO_UNLOCK_SSMI", - [12] = "MCSMI", - [13] = "TCO", - [14] = "PERIODIC", - [15] = "SERIRQ", - [16] = "SMBUS_SMI", - [17] = "XHCI", - [18] = "HOST_SMBUS", - [19] = "SCS", - [20] = "PCI_EXP_SMI", - [21] = "SCC2", - [25] = "SPI_SSMI", - [26] = "SPI", - [27] = "OCP_CSE", + [BIOS_SMI_STS] = "BIOS", + [LEGACY_USB_SMI_STS] = "LEGACY USB", + [SLP_SMI_STS] = "SLP_SMI", + [APM_SMI_STS] = "APM", + [SWSMI_TMR_SMI_STS] = "SWSMI_TMR", + [GPIO_SMI_STS]= "GPIO_SMI", + [GPIO_UNLOCK_SMI_STS]= "GPIO_UNLOCK_SSMI", + [MC_SMI_STS] = "MCSMI", + [TCO_SMI_STS] = "TCO", + [PERIODIC_SMI_STS] = "PERIODIC", + [SERIRQ_SMI_STS] = "SERIRQ", + [SMBUS_SMI_STS] = "SMBUS_SMI", + [XHCI_SMI_STS] = "XHCI", + [HSMBUS_SMI_STS] = "HOST_SMBUS", + [SCS_SMI_STS] = "SCS", + [PCIE_SMI_STS] = "PCI_EXP_SMI", + [SCC2_SMI_STS] = "SCC2", + [SPI_SSMI_STS] = "SPI_SSMI", + [SPI_SMI_STS] = "SPI", + [PMC_OCP_SMI_STS] = "OCP_CSE", }; if (!smi_sts) diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 580fd71d1f..fd175e30d8 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -44,36 +44,8 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void) } const smi_handler_t southbridge_smi[32] = { - NULL, /* [0] reserved */ - NULL, /* [1] reserved */ - NULL, /* [2] BIOS_STS */ - NULL, /* [3] LEGACY_USB_STS */ - southbridge_smi_sleep, /* [4] SLP_SMI_STS */ - southbridge_smi_apmc, /* [5] APM_STS */ - NULL, /* [6] SWSMI_TMR_STS */ - NULL, /* [7] reserved */ - southbridge_smi_pm1, /* [8] PM1_STS */ - southbridge_smi_gpe0, /* [9] GPE0_STS */ - NULL, /* [10] reserved */ - NULL, /* [11] reserved */ - NULL, /* [12] reserved */ - southbridge_smi_tco, /* [13] TCO_STS */ - southbridge_smi_periodic, /* [14] PERIODIC_STS */ - NULL, /* [15] SERIRQ_SMI_STS */ - NULL, /* [16] SMBUS_SMI_STS */ - NULL, /* [17] LEGACY_USB2_STS */ - NULL, /* [18] INTEL_USB2_STS */ - NULL, /* [19] reserved */ - NULL, /* [20] PCI_EXP_SMI_STS */ - NULL, /* [21] reserved */ - NULL, /* [22] reserved */ - NULL, /* [23] reserved */ - NULL, /* [24] reserved */ - NULL, /* [25] reserved */ - NULL, /* [26] SPI_STS */ - NULL, /* [27] reserved */ - NULL, /* [28] PUNIT */ - NULL, /* [29] GUNIT */ - NULL, /* [30] reserved */ - NULL /* [31] reserved */ + [SLP_SMI_STS] = southbridge_smi_sleep, + [APM_SMI_STS] = southbridge_smi_apmc, + [TCO_SMI_STS] = southbridge_smi_tco, + [PERIODIC_SMI_STS] = southbridge_smi_periodic, }; |