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-rw-r--r--src/northbridge/intel/sandybridge/udelay.c22
1 files changed, 16 insertions, 6 deletions
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
index 3d8ba96d75..6ceea40940 100644
--- a/src/northbridge/intel/sandybridge/udelay.c
+++ b/src/northbridge/intel/sandybridge/udelay.c
@@ -23,9 +23,22 @@
#include <cpu/x86/msr.h>
/**
- * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
+ * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz
*/
+/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow.
+ * This code is used to prevent use of libgcc's umoddi3.
+ */
+static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
+{
+ tsc->lo = (a & 0xffff) * (b & 0xffff);
+ tsc->hi = ((tsc->lo >> 16)
+ + ((a & 0xffff) * (b >> 16))
+ + ((b & 0xffff) * (a >> 16)));
+ tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff);
+ tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
+}
+
void udelay(u32 us)
{
u32 dword;
@@ -33,15 +46,12 @@ void udelay(u32 us)
msr_t msr;
u32 fsb = 100, divisor;
u32 d; /* ticks per us */
- u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */
msr = rdmsr(0xce);
divisor = (msr.lo >> 8) & 0xff;
- d = fsb * divisor;
-
- tscd.hi = us / dn;
- tscd.lo = (us - tscd.hi * dn) * d;
+ d = fsb * divisor; /* On Core/Core2 this is divided by 4 */
+ multiply_to_tsc(&tscd, us, d);
tsc1 = rdtsc();
dword = tsc1.lo + tscd.lo;