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-rw-r--r--src/soc/intel/cannonlake/acpi/pci_irqs.asl2
-rw-r--r--src/soc/intel/cannonlake/lpc.c70
-rw-r--r--src/soc/intel/common/block/include/intelblocks/lpc_lib.h4
-rw-r--r--src/soc/intel/common/block/lpc/lpc_lib.c71
-rw-r--r--src/soc/intel/elkhartlake/espi.c70
-rw-r--r--src/soc/intel/icelake/espi.c70
-rw-r--r--src/soc/intel/jasperlake/espi.c70
-rw-r--r--src/soc/intel/skylake/irq.c68
-rw-r--r--src/soc/intel/skylake/lpc.c2
-rw-r--r--src/soc/intel/tigerlake/espi.c70
10 files changed, 79 insertions, 418 deletions
diff --git a/src/soc/intel/cannonlake/acpi/pci_irqs.asl b/src/soc/intel/cannonlake/acpi/pci_irqs.asl
index d35f4d76b9..17e3aa51c6 100644
--- a/src/soc/intel/cannonlake/acpi/pci_irqs.asl
+++ b/src/soc/intel/cannonlake/acpi/pci_irqs.asl
@@ -76,7 +76,7 @@ Name (PICP, Package () {
Name (PICN, Package () {
/*
- * If the setting change in soc_pch_pirq_init(), then
+ * If the setting change in pch_pirq_init(), then
* please make the same static IRQ changes here as well.
*/
/* D31: cAVS, SMBus, GbE, Nothpeak */
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index 9d36f32970..e220678cb1 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -90,74 +90,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
-/*
- * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
- * 0x00 - 0000 = Reserved
- * 0x01 - 0001 = Reserved
- * 0x02 - 0010 = Reserved
- * 0x03 - 0011 = IRQ3
- * 0x04 - 0100 = IRQ4
- * 0x05 - 0101 = IRQ5
- * 0x06 - 0110 = IRQ6
- * 0x07 - 0111 = IRQ7
- * 0x08 - 1000 = Reserved
- * 0x09 - 1001 = IRQ9
- * 0x0A - 1010 = IRQ10
- * 0x0B - 1011 = IRQ11
- * 0x0C - 1100 = IRQ12
- * 0x0D - 1101 = Reserved
- * 0x0E - 1110 = IRQ14
- * 0x0F - 1111 = IRQ15
- * PIRQ[n]_ROUT[7] - PIRQ Routing Control
- * 0x80 - The PIRQ is not routed.
- */
-
-void soc_pch_pirq_init(const struct device *dev)
-{
- struct device *irq_dev;
- uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
-
- pch_interrupt_routing[0] = PCH_IRQ11;
- pch_interrupt_routing[1] = PCH_IRQ10;
- pch_interrupt_routing[2] = PCH_IRQ11;
- pch_interrupt_routing[3] = PCH_IRQ11;
- pch_interrupt_routing[4] = PCH_IRQ11;
- pch_interrupt_routing[5] = PCH_IRQ11;
- pch_interrupt_routing[6] = PCH_IRQ11;
- pch_interrupt_routing[7] = PCH_IRQ11;
-
- itss_irq_init(pch_interrupt_routing);
-
- for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
- u8 int_pin = 0, int_line = 0;
-
- if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
- continue;
-
- int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
-
- switch (int_pin) {
- case 1: /* INTA# */
- int_line = PCH_IRQ11;
- break;
- case 2: /* INTB# */
- int_line = PCH_IRQ10;
- break;
- case 3: /* INTC# */
- int_line = PCH_IRQ11;
- break;
- case 4: /* INTD# */
- int_line = PCH_IRQ11;
- break;
- }
-
- if (!int_line)
- continue;
-
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
- }
-}
-
static void pch_misc_init(void)
{
uint8_t reg8;
@@ -186,7 +118,7 @@ void lpc_soc_init(struct device *dev)
/* Interrupt configuration */
pch_enable_ioapic();
- soc_pch_pirq_init(dev);
+ pch_pirq_init();
setup_i8259();
i8259_configure_irq_trigger(9, 1);
soc_mirror_dmi_pcr_io_dec();
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index 5bbc384e82..52b0ff8e72 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -97,8 +97,6 @@ void lpc_disable_clkrun(void);
void lpc_io_setup_comm_a_b(void);
/* Enable PCH LPC by setting up generic decode range registers. */
void pch_enable_lpc(void);
-/* Retrieve and setup SoC specific PCH LPC interrupt routing. */
-void soc_pch_pirq_init(const struct device *dev);
/* Get SoC's generic IO decoder range register settings. */
void soc_get_gen_io_dec_range(const struct device *dev,
uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]);
@@ -109,5 +107,7 @@ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
uintptr_t base, size_t size, unsigned long flags);
/* Enable PCH IOAPIC */
void pch_enable_ioapic(void);
+/* Retrieve and setup PCH LPC interrupt routing. */
+void pch_pirq_init(void);
#endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 87ee11056e..d189a5e398 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -7,9 +7,11 @@
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ops.h>
+#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
#include <lib.h>
#include "lpc_def.h"
+#include <soc/irq.h>
#include <soc/pci_devs.h>
uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)
@@ -280,7 +282,7 @@ void pch_enable_lpc(void)
lpc_set_gen_decode_range(gen_io_dec);
soc_setup_dmi_pcr_io_dec(gen_io_dec);
if (ENV_PAYLOAD_LOADER)
- soc_pch_pirq_init(dev);
+ pch_pirq_init();
}
void lpc_enable_pci_clk_cntl(void)
@@ -317,3 +319,70 @@ void pch_enable_ioapic(void)
*/
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
+
+/*
+ * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
+ * 0x00 - 0000 = Reserved
+ * 0x01 - 0001 = Reserved
+ * 0x02 - 0010 = Reserved
+ * 0x03 - 0011 = IRQ3
+ * 0x04 - 0100 = IRQ4
+ * 0x05 - 0101 = IRQ5
+ * 0x06 - 0110 = IRQ6
+ * 0x07 - 0111 = IRQ7
+ * 0x08 - 1000 = Reserved
+ * 0x09 - 1001 = IRQ9
+ * 0x0A - 1010 = IRQ10
+ * 0x0B - 1011 = IRQ11
+ * 0x0C - 1100 = IRQ12
+ * 0x0D - 1101 = Reserved
+ * 0x0E - 1110 = IRQ14
+ * 0x0F - 1111 = IRQ15
+ * PIRQ[n]_ROUT[7] - PIRQ Routing Control
+ * 0x80 - The PIRQ is not routed.
+ */
+void pch_pirq_init(void)
+{
+ const struct device *irq_dev;
+ uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
+
+ pch_interrupt_routing[0] = PCH_IRQ11;
+ pch_interrupt_routing[1] = PCH_IRQ10;
+ pch_interrupt_routing[2] = PCH_IRQ11;
+ pch_interrupt_routing[3] = PCH_IRQ11;
+ pch_interrupt_routing[4] = PCH_IRQ11;
+ pch_interrupt_routing[5] = PCH_IRQ11;
+ pch_interrupt_routing[6] = PCH_IRQ11;
+ pch_interrupt_routing[7] = PCH_IRQ11;
+
+ itss_irq_init(pch_interrupt_routing);
+
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ uint8_t int_pin = 0, int_line = 0;
+
+ if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+ continue;
+
+ int_pin = pci_read_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_PIN);
+
+ switch (int_pin) {
+ case 1: /* INTA# */
+ int_line = PCH_IRQ11;
+ break;
+ case 2: /* INTB# */
+ int_line = PCH_IRQ10;
+ break;
+ case 3: /* INTC# */
+ int_line = PCH_IRQ11;
+ break;
+ case 4: /* INTD# */
+ int_line = PCH_IRQ11;
+ break;
+ }
+
+ if (!int_line)
+ continue;
+
+ pci_write_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_LINE, int_line);
+ }
+}
diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c
index 241262344f..6e6f887842 100644
--- a/src/soc/intel/elkhartlake/espi.c
+++ b/src/soc/intel/elkhartlake/espi.c
@@ -64,74 +64,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
-/*
- * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
- * 0x00 - 0000 = Reserved
- * 0x01 - 0001 = Reserved
- * 0x02 - 0010 = Reserved
- * 0x03 - 0011 = IRQ3
- * 0x04 - 0100 = IRQ4
- * 0x05 - 0101 = IRQ5
- * 0x06 - 0110 = IRQ6
- * 0x07 - 0111 = IRQ7
- * 0x08 - 1000 = Reserved
- * 0x09 - 1001 = IRQ9
- * 0x0A - 1010 = IRQ10
- * 0x0B - 1011 = IRQ11
- * 0x0C - 1100 = IRQ12
- * 0x0D - 1101 = Reserved
- * 0x0E - 1110 = IRQ14
- * 0x0F - 1111 = IRQ15
- * PIRQ[n]_ROUT[7] - PIRQ Routing Control
- * 0x80 - The PIRQ is not routed.
- */
-
-void soc_pch_pirq_init(const struct device *dev)
-{
- struct device *irq_dev;
- uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
-
- pch_interrupt_routing[0] = PCH_IRQ11;
- pch_interrupt_routing[1] = PCH_IRQ10;
- pch_interrupt_routing[2] = PCH_IRQ11;
- pch_interrupt_routing[3] = PCH_IRQ11;
- pch_interrupt_routing[4] = PCH_IRQ11;
- pch_interrupt_routing[5] = PCH_IRQ11;
- pch_interrupt_routing[6] = PCH_IRQ11;
- pch_interrupt_routing[7] = PCH_IRQ11;
-
- itss_irq_init(pch_interrupt_routing);
-
- for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
- uint8_t int_pin = 0, int_line = 0;
-
- if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
- continue;
-
- int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
-
- switch (int_pin) {
- case 1: /* INTA# */
- int_line = PCH_IRQ11;
- break;
- case 2: /* INTB# */
- int_line = PCH_IRQ10;
- break;
- case 3: /* INTC# */
- int_line = PCH_IRQ11;
- break;
- case 4: /* INTD# */
- int_line = PCH_IRQ11;
- break;
- }
-
- if (!int_line)
- continue;
-
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
- }
-}
-
static void pch_misc_init(void)
{
uint8_t reg8;
@@ -161,7 +93,7 @@ void lpc_soc_init(struct device *dev)
/* Interrupt configuration */
pch_enable_ioapic();
- soc_pch_pirq_init(dev);
+ pch_pirq_init();
setup_i8259();
i8259_configure_irq_trigger(9, 1);
soc_mirror_dmi_pcr_io_dec();
diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c
index bf5c50d7f6..388d9fa503 100644
--- a/src/soc/intel/icelake/espi.c
+++ b/src/soc/intel/icelake/espi.c
@@ -83,74 +83,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
-/*
- * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
- * 0x00 - 0000 = Reserved
- * 0x01 - 0001 = Reserved
- * 0x02 - 0010 = Reserved
- * 0x03 - 0011 = IRQ3
- * 0x04 - 0100 = IRQ4
- * 0x05 - 0101 = IRQ5
- * 0x06 - 0110 = IRQ6
- * 0x07 - 0111 = IRQ7
- * 0x08 - 1000 = Reserved
- * 0x09 - 1001 = IRQ9
- * 0x0A - 1010 = IRQ10
- * 0x0B - 1011 = IRQ11
- * 0x0C - 1100 = IRQ12
- * 0x0D - 1101 = Reserved
- * 0x0E - 1110 = IRQ14
- * 0x0F - 1111 = IRQ15
- * PIRQ[n]_ROUT[7] - PIRQ Routing Control
- * 0x80 - The PIRQ is not routed.
- */
-
-void soc_pch_pirq_init(const struct device *dev)
-{
- struct device *irq_dev;
- uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
-
- pch_interrupt_routing[0] = PCH_IRQ11;
- pch_interrupt_routing[1] = PCH_IRQ10;
- pch_interrupt_routing[2] = PCH_IRQ11;
- pch_interrupt_routing[3] = PCH_IRQ11;
- pch_interrupt_routing[4] = PCH_IRQ11;
- pch_interrupt_routing[5] = PCH_IRQ11;
- pch_interrupt_routing[6] = PCH_IRQ11;
- pch_interrupt_routing[7] = PCH_IRQ11;
-
- itss_irq_init(pch_interrupt_routing);
-
- for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
- u8 int_pin = 0, int_line = 0;
-
- if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
- continue;
-
- int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
-
- switch (int_pin) {
- case 1: /* INTA# */
- int_line = PCH_IRQ11;
- break;
- case 2: /* INTB# */
- int_line = PCH_IRQ10;
- break;
- case 3: /* INTC# */
- int_line = PCH_IRQ11;
- break;
- case 4: /* INTD# */
- int_line = PCH_IRQ11;
- break;
- }
-
- if (!int_line)
- continue;
-
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
- }
-}
-
static void pch_misc_init(void)
{
uint8_t reg8;
@@ -180,7 +112,7 @@ void lpc_soc_init(struct device *dev)
/* Interrupt configuration */
pch_enable_ioapic();
- soc_pch_pirq_init(dev);
+ pch_pirq_init();
setup_i8259();
i8259_configure_irq_trigger(9, 1);
soc_mirror_dmi_pcr_io_dec();
diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c
index 24b50579fc..ef1ed953fb 100644
--- a/src/soc/intel/jasperlake/espi.c
+++ b/src/soc/intel/jasperlake/espi.c
@@ -65,74 +65,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
-/*
- * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
- * 0x00 - 0000 = Reserved
- * 0x01 - 0001 = Reserved
- * 0x02 - 0010 = Reserved
- * 0x03 - 0011 = IRQ3
- * 0x04 - 0100 = IRQ4
- * 0x05 - 0101 = IRQ5
- * 0x06 - 0110 = IRQ6
- * 0x07 - 0111 = IRQ7
- * 0x08 - 1000 = Reserved
- * 0x09 - 1001 = IRQ9
- * 0x0A - 1010 = IRQ10
- * 0x0B - 1011 = IRQ11
- * 0x0C - 1100 = IRQ12
- * 0x0D - 1101 = Reserved
- * 0x0E - 1110 = IRQ14
- * 0x0F - 1111 = IRQ15
- * PIRQ[n]_ROUT[7] - PIRQ Routing Control
- * 0x80 - The PIRQ is not routed.
- */
-
-void soc_pch_pirq_init(const struct device *dev)
-{
- struct device *irq_dev;
- uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
-
- pch_interrupt_routing[0] = PCH_IRQ11;
- pch_interrupt_routing[1] = PCH_IRQ10;
- pch_interrupt_routing[2] = PCH_IRQ11;
- pch_interrupt_routing[3] = PCH_IRQ11;
- pch_interrupt_routing[4] = PCH_IRQ11;
- pch_interrupt_routing[5] = PCH_IRQ11;
- pch_interrupt_routing[6] = PCH_IRQ11;
- pch_interrupt_routing[7] = PCH_IRQ11;
-
- itss_irq_init(pch_interrupt_routing);
-
- for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
- u8 int_pin = 0, int_line = 0;
-
- if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
- continue;
-
- int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
-
- switch (int_pin) {
- case 1: /* INTA# */
- int_line = PCH_IRQ11;
- break;
- case 2: /* INTB# */
- int_line = PCH_IRQ10;
- break;
- case 3: /* INTC# */
- int_line = PCH_IRQ11;
- break;
- case 4: /* INTD# */
- int_line = PCH_IRQ11;
- break;
- }
-
- if (!int_line)
- continue;
-
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
- }
-}
-
static void pch_misc_init(void)
{
uint8_t reg8;
@@ -162,7 +94,7 @@ void lpc_soc_init(struct device *dev)
/* Interrupt configuration */
pch_enable_ioapic();
- soc_pch_pirq_init(dev);
+ pch_pirq_init();
setup_i8259();
i8259_configure_irq_trigger(9, 1);
soc_mirror_dmi_pcr_io_dec();
diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c
index 62050c9782..ad75f027a1 100644
--- a/src/soc/intel/skylake/irq.c
+++ b/src/soc/intel/skylake/irq.c
@@ -215,71 +215,3 @@ void soc_irq_settings(FSP_SIL_UPD *params)
/* TCO Irq enable/disable */
params->TcoIrqEnable = config->TcoIrqEnable;
}
-
-/*
- * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
- * 0x00 - 0000 = Reserved
- * 0x01 - 0001 = Reserved
- * 0x02 - 0010 = Reserved
- * 0x03 - 0011 = IRQ3
- * 0x04 - 0100 = IRQ4
- * 0x05 - 0101 = IRQ5
- * 0x06 - 0110 = IRQ6
- * 0x07 - 0111 = IRQ7
- * 0x08 - 1000 = Reserved
- * 0x09 - 1001 = IRQ9
- * 0x0A - 1010 = IRQ10
- * 0x0B - 1011 = IRQ11
- * 0x0C - 1100 = IRQ12
- * 0x0D - 1101 = Reserved
- * 0x0E - 1110 = IRQ14
- * 0x0F - 1111 = IRQ15
- * PIRQ[n]_ROUT[7] - PIRQ Routing Control
- * 0x80 - The PIRQ is not routed.
- */
-
-void soc_pch_pirq_init(const struct device *dev)
-{
- uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
- struct device *irq_dev;
-
- pch_interrupt_routing[0] = PCH_IRQ11;
- pch_interrupt_routing[1] = PCH_IRQ10;
- pch_interrupt_routing[2] = PCH_IRQ11;
- pch_interrupt_routing[3] = PCH_IRQ11;
- pch_interrupt_routing[4] = PCH_IRQ11;
- pch_interrupt_routing[5] = PCH_IRQ11;
- pch_interrupt_routing[6] = PCH_IRQ11;
- pch_interrupt_routing[7] = PCH_IRQ11;
-
- itss_irq_init(pch_interrupt_routing);
-
- for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
- u8 int_pin = 0, int_line = 0;
-
- if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
- continue;
-
- int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
-
- switch (int_pin) {
- case 1: /* INTA# */
- int_line = PCH_IRQ11;
- break;
- case 2: /* INTB# */
- int_line = PCH_IRQ10;
- break;
- case 3: /* INTC# */
- int_line = PCH_IRQ11;
- break;
- case 4: /* INTD# */
- int_line = PCH_IRQ11;
- break;
- }
-
- if (!int_line)
- continue;
-
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
- }
-}
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index e514e1a66a..0eaeb9ff93 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -74,7 +74,7 @@ void lpc_soc_init(struct device *dev)
/* Interrupt configuration */
pch_enable_ioapic();
- soc_pch_pirq_init(dev);
+ pch_pirq_init();
setup_i8259();
i8259_configure_irq_trigger(9, 1);
}
diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c
index eb44a6a65d..668e95f41d 100644
--- a/src/soc/intel/tigerlake/espi.c
+++ b/src/soc/intel/tigerlake/espi.c
@@ -71,74 +71,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
-/*
- * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
- * 0x00 - 0000 = Reserved
- * 0x01 - 0001 = Reserved
- * 0x02 - 0010 = Reserved
- * 0x03 - 0011 = IRQ3
- * 0x04 - 0100 = IRQ4
- * 0x05 - 0101 = IRQ5
- * 0x06 - 0110 = IRQ6
- * 0x07 - 0111 = IRQ7
- * 0x08 - 1000 = Reserved
- * 0x09 - 1001 = IRQ9
- * 0x0A - 1010 = IRQ10
- * 0x0B - 1011 = IRQ11
- * 0x0C - 1100 = IRQ12
- * 0x0D - 1101 = Reserved
- * 0x0E - 1110 = IRQ14
- * 0x0F - 1111 = IRQ15
- * PIRQ[n]_ROUT[7] - PIRQ Routing Control
- * 0x80 - The PIRQ is not routed.
- */
-
-void soc_pch_pirq_init(const struct device *dev)
-{
- struct device *irq_dev;
- uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
-
- pch_interrupt_routing[0] = PCH_IRQ11;
- pch_interrupt_routing[1] = PCH_IRQ10;
- pch_interrupt_routing[2] = PCH_IRQ11;
- pch_interrupt_routing[3] = PCH_IRQ11;
- pch_interrupt_routing[4] = PCH_IRQ11;
- pch_interrupt_routing[5] = PCH_IRQ11;
- pch_interrupt_routing[6] = PCH_IRQ11;
- pch_interrupt_routing[7] = PCH_IRQ11;
-
- itss_irq_init(pch_interrupt_routing);
-
- for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
- u8 int_pin = 0, int_line = 0;
-
- if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
- continue;
-
- int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
-
- switch (int_pin) {
- case 1: /* INTA# */
- int_line = PCH_IRQ11;
- break;
- case 2: /* INTB# */
- int_line = PCH_IRQ10;
- break;
- case 3: /* INTC# */
- int_line = PCH_IRQ11;
- break;
- case 4: /* INTD# */
- int_line = PCH_IRQ11;
- break;
- }
-
- if (!int_line)
- continue;
-
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
- }
-}
-
static void pch_misc_init(void)
{
uint8_t reg8;
@@ -168,7 +100,7 @@ void lpc_soc_init(struct device *dev)
/* Interrupt configuration */
pch_enable_ioapic();
- soc_pch_pirq_init(dev);
+ pch_pirq_init();
setup_i8259();
i8259_configure_irq_trigger(9, 1);
soc_mirror_dmi_pcr_io_dec();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 01:17:00 +0000