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-rw-r--r--src/soc/intel/skylake/acpi.c109
-rw-r--r--src/soc/intel/skylake/chip.c111
2 files changed, 111 insertions, 109 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index c2eb9a8d36..0d89f29e7e 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -548,112 +548,3 @@ int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint
return GPE0_REG_MAX;
}
-
-const char *soc_acpi_name(const struct device *dev)
-{
- if (dev->path.type == DEVICE_PATH_DOMAIN)
- return "PCI0";
-
- if (dev->path.type == DEVICE_PATH_USB) {
- switch (dev->path.usb.port_type) {
- case 0:
- /* Root Hub */
- return "RHUB";
- case 2:
- /* USB2 ports */
- switch (dev->path.usb.port_id) {
- case 0: return "HS01";
- case 1: return "HS02";
- case 2: return "HS03";
- case 3: return "HS04";
- case 4: return "HS05";
- case 5: return "HS06";
- case 6: return "HS07";
- case 7: return "HS08";
- case 8: return "HS09";
- case 9: return "HS10";
- }
- break;
- case 3:
- /* USB3 ports */
- switch (dev->path.usb.port_id) {
- case 0: return "SS01";
- case 1: return "SS02";
- case 2: return "SS03";
- case 3: return "SS04";
- case 4: return "SS05";
- case 5: return "SS06";
- }
- break;
- }
- return NULL;
- }
-
- if (dev->path.type != DEVICE_PATH_PCI)
- return NULL;
-
- /* Match functions 0 and 1 for possible GPUs on a secondary bus */
- if (dev->bus && dev->bus->secondary > 0) {
- switch (PCI_FUNC(dev->path.pci.devfn)) {
- case 0: return "DEV0";
- case 1: return "DEV1";
- }
- return NULL;
- }
-
- switch (dev->path.pci.devfn) {
- case SA_DEVFN_ROOT: return "MCHC";
- case SA_DEVFN_PEG0: return "PEGP";
- case SA_DEVFN_IGD: return "GFX0";
- case PCH_DEVFN_ISH: return "ISHB";
- case PCH_DEVFN_XHCI: return "XHCI";
- case PCH_DEVFN_USBOTG: return "XDCI";
- case PCH_DEVFN_THERMAL: return "THRM";
- case PCH_DEVFN_CIO: return "ICIO";
- case PCH_DEVFN_I2C0: return "I2C0";
- case PCH_DEVFN_I2C1: return "I2C1";
- case PCH_DEVFN_I2C2: return "I2C2";
- case PCH_DEVFN_I2C3: return "I2C3";
- case PCH_DEVFN_CSE: return "CSE1";
- case PCH_DEVFN_CSE_2: return "CSE2";
- case PCH_DEVFN_CSE_IDER: return "CSED";
- case PCH_DEVFN_CSE_KT: return "CSKT";
- case PCH_DEVFN_CSE_3: return "CSE3";
- case PCH_DEVFN_SATA: return "SATA";
- case PCH_DEVFN_UART2: return "UAR2";
- case PCH_DEVFN_I2C4: return "I2C4";
- case PCH_DEVFN_I2C5: return "I2C5";
- case PCH_DEVFN_PCIE1: return "RP01";
- case PCH_DEVFN_PCIE2: return "RP02";
- case PCH_DEVFN_PCIE3: return "RP03";
- case PCH_DEVFN_PCIE4: return "RP04";
- case PCH_DEVFN_PCIE5: return "RP05";
- case PCH_DEVFN_PCIE6: return "RP06";
- case PCH_DEVFN_PCIE7: return "RP07";
- case PCH_DEVFN_PCIE8: return "RP08";
- case PCH_DEVFN_PCIE9: return "RP09";
- case PCH_DEVFN_PCIE10: return "RP10";
- case PCH_DEVFN_PCIE11: return "RP11";
- case PCH_DEVFN_PCIE12: return "RP12";
- case PCH_DEVFN_PCIE13: return "RP13";
- case PCH_DEVFN_PCIE14: return "RP14";
- case PCH_DEVFN_PCIE15: return "RP15";
- case PCH_DEVFN_PCIE16: return "RP16";
- case PCH_DEVFN_UART0: return "UAR0";
- case PCH_DEVFN_UART1: return "UAR1";
- case PCH_DEVFN_GSPI0: return "SPI0";
- case PCH_DEVFN_GSPI1: return "SPI1";
- case PCH_DEVFN_EMMC: return "EMMC";
- case PCH_DEVFN_SDIO: return "SDIO";
- case PCH_DEVFN_SDCARD: return "SDXC";
- case PCH_DEVFN_P2SB: return "P2SB";
- case PCH_DEVFN_PMC: return "PMC_";
- case PCH_DEVFN_HDA: return "HDAS";
- case PCH_DEVFN_SMBUS: return "SBUS";
- case PCH_DEVFN_SPI: return "FSPI";
- case PCH_DEVFN_GBE: return "IGBE";
- case PCH_DEVFN_TRACEHUB:return "THUB";
- }
-
- return NULL;
-}
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 728b023c70..0ae98a9e0d 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -48,6 +48,117 @@ static const struct pcie_rp_group pch_h_rp_groups[] = {
{ 0 }
};
+#if CONFIG(HAVE_ACPI_TABLES)
+const char *soc_acpi_name(const struct device *dev)
+{
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ return "PCI0";
+
+ if (dev->path.type == DEVICE_PATH_USB) {
+ switch (dev->path.usb.port_type) {
+ case 0:
+ /* Root Hub */
+ return "RHUB";
+ case 2:
+ /* USB2 ports */
+ switch (dev->path.usb.port_id) {
+ case 0: return "HS01";
+ case 1: return "HS02";
+ case 2: return "HS03";
+ case 3: return "HS04";
+ case 4: return "HS05";
+ case 5: return "HS06";
+ case 6: return "HS07";
+ case 7: return "HS08";
+ case 8: return "HS09";
+ case 9: return "HS10";
+ }
+ break;
+ case 3:
+ /* USB3 ports */
+ switch (dev->path.usb.port_id) {
+ case 0: return "SS01";
+ case 1: return "SS02";
+ case 2: return "SS03";
+ case 3: return "SS04";
+ case 4: return "SS05";
+ case 5: return "SS06";
+ }
+ break;
+ }
+ return NULL;
+ }
+
+ if (dev->path.type != DEVICE_PATH_PCI)
+ return NULL;
+
+ /* Match functions 0 and 1 for possible GPUs on a secondary bus */
+ if (dev->bus && dev->bus->secondary > 0) {
+ switch (PCI_FUNC(dev->path.pci.devfn)) {
+ case 0: return "DEV0";
+ case 1: return "DEV1";
+ }
+ return NULL;
+ }
+
+ switch (dev->path.pci.devfn) {
+ case SA_DEVFN_ROOT: return "MCHC";
+ case SA_DEVFN_PEG0: return "PEGP";
+ case SA_DEVFN_IGD: return "GFX0";
+ case PCH_DEVFN_ISH: return "ISHB";
+ case PCH_DEVFN_XHCI: return "XHCI";
+ case PCH_DEVFN_USBOTG: return "XDCI";
+ case PCH_DEVFN_THERMAL: return "THRM";
+ case PCH_DEVFN_CIO: return "ICIO";
+ case PCH_DEVFN_I2C0: return "I2C0";
+ case PCH_DEVFN_I2C1: return "I2C1";
+ case PCH_DEVFN_I2C2: return "I2C2";
+ case PCH_DEVFN_I2C3: return "I2C3";
+ case PCH_DEVFN_CSE: return "CSE1";
+ case PCH_DEVFN_CSE_2: return "CSE2";
+ case PCH_DEVFN_CSE_IDER: return "CSED";
+ case PCH_DEVFN_CSE_KT: return "CSKT";
+ case PCH_DEVFN_CSE_3: return "CSE3";
+ case PCH_DEVFN_SATA: return "SATA";
+ case PCH_DEVFN_UART2: return "UAR2";
+ case PCH_DEVFN_I2C4: return "I2C4";
+ case PCH_DEVFN_I2C5: return "I2C5";
+ case PCH_DEVFN_PCIE1: return "RP01";
+ case PCH_DEVFN_PCIE2: return "RP02";
+ case PCH_DEVFN_PCIE3: return "RP03";
+ case PCH_DEVFN_PCIE4: return "RP04";
+ case PCH_DEVFN_PCIE5: return "RP05";
+ case PCH_DEVFN_PCIE6: return "RP06";
+ case PCH_DEVFN_PCIE7: return "RP07";
+ case PCH_DEVFN_PCIE8: return "RP08";
+ case PCH_DEVFN_PCIE9: return "RP09";
+ case PCH_DEVFN_PCIE10: return "RP10";
+ case PCH_DEVFN_PCIE11: return "RP11";
+ case PCH_DEVFN_PCIE12: return "RP12";
+ case PCH_DEVFN_PCIE13: return "RP13";
+ case PCH_DEVFN_PCIE14: return "RP14";
+ case PCH_DEVFN_PCIE15: return "RP15";
+ case PCH_DEVFN_PCIE16: return "RP16";
+ case PCH_DEVFN_UART0: return "UAR0";
+ case PCH_DEVFN_UART1: return "UAR1";
+ case PCH_DEVFN_GSPI0: return "SPI0";
+ case PCH_DEVFN_GSPI1: return "SPI1";
+ case PCH_DEVFN_EMMC: return "EMMC";
+ case PCH_DEVFN_SDIO: return "SDIO";
+ case PCH_DEVFN_SDCARD: return "SDXC";
+ case PCH_DEVFN_P2SB: return "P2SB";
+ case PCH_DEVFN_PMC: return "PMC_";
+ case PCH_DEVFN_HDA: return "HDAS";
+ case PCH_DEVFN_SMBUS: return "SBUS";
+ case PCH_DEVFN_SPI: return "FSPI";
+ case PCH_DEVFN_GBE: return "IGBE";
+ case PCH_DEVFN_TRACEHUB:return "THUB";
+ }
+
+ return NULL;
+}
+#endif
+
void soc_init_pre_device(void *chip_info)
{
/* Snapshot the current GPIO IRQ polarities. FSP is setting a
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 20:08:20 +0000