diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/guybrush/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/guybrush/variants/guybrush/overridetree.cb | 27 |
3 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index c9f8fe0b37..77e4a195af 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -9,6 +9,8 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select AMD_SOC_CONSOLE_UART select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index fa15509f44..3205d21680 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -38,6 +38,9 @@ chip soc/amd/cezanne .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), }" + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | + GPIO_I2C2_SCL | GPIO_I2C3_SCL" + device domain 0 on device ref gpp_bridge_0 on end # WLAN device ref gpp_bridge_1 on end # SD diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb index 80c04ee7ed..286ba28c45 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb @@ -34,4 +34,31 @@ end chip soc/amd/cezanne device domain 0 on end # domain + + # I2C Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | Speaker, Codec, P-SAR | + #| I2C3 | H1/D2 TPM | + #+-------------------+---------------------------+ + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + }" + + register "i2c[1]" = "{ + .speed = I2C_SPEED_FAST, + }" + + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + }" + + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .early_init = true, + }" + end # chip soc/amd/cezanne |