diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index d6e7ee9025..71b8e12782 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -10,6 +10,9 @@ #include <device/pci_def.h> #include <device/device.h> #include <northbridge/intel/sandybridge/chip.h> +#include <security/intel/txt/txt.h> +#include <security/intel/txt/txt_platform.h> +#include <security/intel/txt/txt_register.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/pmclib.h> #include <elog.h> @@ -22,6 +25,21 @@ __weak void mainboard_late_rcba_config(void) { } +static void configure_dpr(void) +{ + union dpr_register dpr = txt_get_chipset_dpr(); + + /* + * Just need to program the size of DPR, enable and lock it. + * The dpr.top will always point to TSEG_BASE (updated by hardware). + * We do it early because it will be needed later to calculate cbmem_top. + */ + dpr.lock = 1; + dpr.epm = 1; + dpr.size = CONFIG_INTEL_TXT_DPR_SIZE; + pci_write_config32(HOST_BRIDGE, DPR, dpr.raw); +} + static void early_pch_reset_pmcon(void) { /* Reset RTC power status */ @@ -60,6 +78,11 @@ void mainboard_romstage_entry(void) post_code(0x39); + if (CONFIG(INTEL_TXT)) { + configure_dpr(); + intel_txt_romstage_init(); + } + perform_raminit(s3resume); post_code(0x3b); |