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-rw-r--r--src/drivers/usb/pci_ehci.c6
-rw-r--r--src/include/device/pci_ehci.h5
-rw-r--r--src/soc/amd/stoneyridge/enable_usbdebug.c12
-rw-r--r--src/soc/intel/broadwell/usb_debug.c13
-rw-r--r--src/southbridge/amd/agesa/hudson/enable_usbdebug.c12
-rw-r--r--src/southbridge/amd/pi/hudson/enable_usbdebug.c12
-rw-r--r--src/southbridge/amd/sb600/enable_usbdebug.c4
-rw-r--r--src/southbridge/amd/sb700/enable_usbdebug.c4
-rw-r--r--src/southbridge/amd/sb800/enable_usbdebug.c12
-rw-r--r--src/southbridge/intel/common/usb_debug.c28
-rw-r--r--src/southbridge/nvidia/ck804/enable_usbdebug.c4
-rw-r--r--src/southbridge/nvidia/mcp55/enable_usbdebug.c4
-rw-r--r--src/southbridge/sis/sis966/enable_usbdebug.c4
13 files changed, 33 insertions, 87 deletions
diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c
index 8b72f57a5a..9099976ad5 100644
--- a/src/drivers/usb/pci_ehci.c
+++ b/src/drivers/usb/pci_ehci.c
@@ -33,13 +33,17 @@ static struct device_operations ehci_dbg_ops;
int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
{
pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
- pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR);
+
#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = dbg_dev;
#else
device_t dev = dev_find_slot(PCI_DEV2SEGBUS(dbg_dev), PCI_DEV2DEVFN(dbg_dev));
#endif
+ u32 class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
+ if (class != PCI_EHCI_CLASSCODE)
+ return -1;
+
u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG);
if (!pos)
return -1;
diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h
index 48178c8e1f..9d18bcc798 100644
--- a/src/include/device/pci_ehci.h
+++ b/src/include/device/pci_ehci.h
@@ -23,10 +23,13 @@
#define EHCI_BAR_INDEX 0x10
#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
+/* Return PCI BDF for an EHCI controller by a given index. PCI function
+ * must already be powered to respond to configuration requests.
+ */
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx);
+
u8 *pci_ehci_base_regs(pci_devfn_t dev);
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port);
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base);
#ifndef __PRE_RAM__
#if !IS_ENABLED(CONFIG_USBDEBUG)
diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c
index db1e4cf231..7ed6721a48 100644
--- a/src/soc/amd/stoneyridge/enable_usbdebug.c
+++ b/src/soc/amd/stoneyridge/enable_usbdebug.c
@@ -26,6 +26,10 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
+ /* Enable all of the USB controllers */
+ outb(0xEF, PM_INDEX);
+ outb(0x7F, PM_DATA);
+
if (hcd_idx == 3)
return PCI_DEV(0, 0x16, 0);
else if (hcd_idx == 2)
@@ -46,11 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
}
-
-
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
-{
- /* Enable all of the USB controllers */
- outb(0xEF, PM_INDEX);
- outb(0x7F, PM_DATA);
-}
diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/usb_debug.c
index b19462dc3e..9580a5c90d 100644
--- a/src/soc/intel/broadwell/usb_debug.c
+++ b/src/soc/intel/broadwell/usb_debug.c
@@ -24,21 +24,10 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
- u32 class;
- pci_devfn_t dev = PCI_DEV(0, 0x1d, 0);
-
- class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
- if (class != PCI_EHCI_CLASSCODE)
- return 0;
-
- return dev;
+ return PCI_DEV(0, 0x1d, 0);
}
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
/* Hardcoded to physical port 1 */
}
-
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
-{
-}
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index 4a37e557b6..88b28f4d32 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -26,6 +26,10 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
+ /* Enable all of the USB controllers */
+ outb(0xEF, PM_INDEX);
+ outb(0x7F, PM_DATA);
+
if (hcd_idx == 3)
return PCI_DEV(0, 0x16, 2);
else if (hcd_idx == 2)
@@ -46,11 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
}
-
-
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
-{
- /* Enable all of the USB controllers */
- outb(0xEF, PM_INDEX);
- outb(0x7F, PM_DATA);
-}
diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c
index cb6961ae40..7bea799d0a 100644
--- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c
@@ -26,6 +26,10 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
+ /* Enable all of the USB controllers */
+ outb(0xEF, PM_INDEX);
+ outb(0x7F, PM_DATA);
+
if (hcd_idx == 3)
return PCI_DEV(0, 0x16, 0);
else if (hcd_idx == 2)
@@ -46,11 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
}
-
-
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
-{
- /* Enable all of the USB controllers */
- outb(0xEF, PM_INDEX);
- outb(0x7F, PM_DATA);
-}
diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c
index 8b19cc41de..5988add889 100644
--- a/src/southbridge/amd/sb600/enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/enable_usbdebug.c
@@ -32,7 +32,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
/* TODO: Allow changing the physical USB port used as Debug Port. */
}
-
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
-{
-}
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index 6d95b8ee4f..654c1acbcf 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -45,7 +45,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
}
-
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
-{
-}
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index 8ef3151f13..938a4a6617 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -26,6 +26,10 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
+ /* Enable all of the USB controllers */
+ outb(0xEF, PM_INDEX);
+ outb(0x7F, PM_DATA);
+
if (hcd_idx == 3)
return PCI_DEV(0, 0x16, 2);
else if (hcd_idx == 2)
@@ -46,11 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
}
-
-
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
-{
- /* Enable all of the USB controllers */
- outb(0xEF, PM_INDEX);
- outb(0x7F, PM_DATA);
-}
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index e1cd6575d0..f74da657fd 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -27,27 +27,20 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
u32 class;
pci_devfn_t dev;
-#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)
+ if (!IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS))
+ return PCI_DEV(0, 0x1d, 7);
+
if (hcd_idx==2)
dev = PCI_DEV(0, 0x1a, 0);
else
dev = PCI_DEV(0, 0x1d, 0);
-#else
- dev = PCI_DEV(0, 0x1d, 7);
-#endif
+ /* If we enter here before RCBA programming, EHCI function may
+ * appear with the highest function number instead.
+ */
class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
-#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)
- if (class != PCI_EHCI_CLASSCODE) {
- /* If we enter here before RCBA programming, EHCI function may
- * appear with the highest function number instead.
- */
- dev |= PCI_DEV(0, 0, 7);
- class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
- }
-#endif
if (class != PCI_EHCI_CLASSCODE)
- return 0;
+ dev |= PCI_DEV(0, 0, 7);
return dev;
}
@@ -57,10 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
/* Not needed, the ICH* southbridges hardcode physical USB port 1. */
}
-
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
-{
- /* Bail out. No console to complain in. */
- if (!dev)
- return;
-}
diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index 4ae4aa0052..7296e0526d 100644
--- a/src/southbridge/nvidia/ck804/enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
@@ -41,7 +41,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
dword |= (port << 12);
pci_write_config32(dev, 0x74, dword);
}
-
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
-{
-}
diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
index 679a71d7b3..69e085984d 100644
--- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
@@ -41,7 +41,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
dword |= (port << 12);
pci_write_config32(dev, 0x74, dword);
}
-
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
-{
-}
diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index 428af9429a..6be115e3e5 100644
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
@@ -43,7 +43,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
dword |= (port << 12);
pci_write_config32(dev, 0x74, dword);
}
-
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
-{
-}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 00:16:07 +0000