diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 52c77be325..2927d12e5a 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -128,34 +128,34 @@ static void save_dimm_info(void) void mainboard_romstage_entry(void) { - bool s3wake; struct chipset_power_state *ps = pmc_get_power_state(); + bool s3wake = pmc_fill_power_state(ps) == ACPI_S3; - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ - systemagent_early_init(); - /* Program SMBus base address and enable it */ - smbus_common_init(); /* Initialize HECI interface */ cse_init(HECI1_BASE_ADDRESS); - /* - * Disable Intel TXT if `CPU is unsupported` or `SoC haven't selected the config`. - * - * It would help to access VGA framebuffer prior calling into FSP-M. - */ - if (!CONFIG(INTEL_TXT)) - disable_intel_txt(); if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) dbg_feature_cntrl_init(); - s3wake = pmc_fill_power_state(ps) == ACPI_S3; - if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) { timestamp_add_now(TS_CSE_FW_SYNC_START); cse_fw_sync(); timestamp_add_now(TS_CSE_FW_SYNC_END); } + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + /* Program SMBus base address and enable it */ + smbus_common_init(); + + /* + * Disable Intel TXT if `CPU is unsupported` or `SoC haven't selected the config`. + * + * It would help to access VGA framebuffer prior calling into FSP-M. + */ + if (!CONFIG(INTEL_TXT)) + disable_intel_txt(); + /* Update coreboot timestamp table with CSE timestamps */ if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY)) cse_get_telemetry_data(); |