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-rw-r--r--src/mainboard/google/auron/chromeos.c3
-rw-r--r--src/mainboard/google/auron/onboard.h9
-rw-r--r--src/mainboard/google/butterfly/chromeos.c3
-rw-r--r--src/mainboard/google/butterfly/onboard.h4
-rw-r--r--src/mainboard/google/link/chromeos.c7
-rw-r--r--src/mainboard/google/link/onboard.h4
-rw-r--r--src/mainboard/google/parrot/chromeos.c21
-rw-r--r--src/mainboard/google/parrot/onboard.h9
-rw-r--r--src/mainboard/google/slippy/chromeos.c5
-rw-r--r--src/mainboard/google/slippy/onboard.h3
-rw-r--r--src/mainboard/google/stout/chromeos.c5
-rw-r--r--src/mainboard/google/stout/onboard.h3
-rw-r--r--src/mainboard/intel/baskingridge/chromeos.c11
-rw-r--r--src/mainboard/intel/baskingridge/onboard.h12
-rw-r--r--src/mainboard/intel/emeraldlake2/chromeos.c11
-rw-r--r--src/mainboard/intel/emeraldlake2/onboard.h12
-rw-r--r--src/mainboard/intel/strago/chromeos.c5
-rw-r--r--src/mainboard/intel/strago/onboard.h3
18 files changed, 92 insertions, 38 deletions
diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c
index 3132fd7da5..40f98f20eb 100644
--- a/src/mainboard/google/auron/chromeos.c
+++ b/src/mainboard/google/auron/chromeos.c
@@ -7,8 +7,7 @@
#include <soc/chromeos.h>
#include <southbridge/intel/lynxpoint/lp_gpio.h>
-/* SPI Write protect is GPIO 16 */
-#define CROS_WP_GPIO 58
+#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios)
{
diff --git a/src/mainboard/google/auron/onboard.h b/src/mainboard/google/auron/onboard.h
new file mode 100644
index 0000000000..6d4ff28dd8
--- /dev/null
+++ b/src/mainboard/google/auron/onboard.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AURON_ONBOARD_H
+#define AURON_ONBOARD_H
+
+/* SPI Write protect is GPIO 58 */
+#define CROS_WP_GPIO 58
+
+#endif
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c
index 2de55b0dff..2293f93d62 100644
--- a/src/mainboard/google/butterfly/chromeos.c
+++ b/src/mainboard/google/butterfly/chromeos.c
@@ -11,9 +11,8 @@
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
+#include "onboard.h"
-#define WP_GPIO 6
-#define DEVMODE_GPIO 54
#define FORCE_RECOVERY_MODE 0
void fill_lb_gpios(struct lb_gpios *gpios)
diff --git a/src/mainboard/google/butterfly/onboard.h b/src/mainboard/google/butterfly/onboard.h
index b8da862d12..f799d04083 100644
--- a/src/mainboard/google/butterfly/onboard.h
+++ b/src/mainboard/google/butterfly/onboard.h
@@ -16,4 +16,8 @@
/* 0x00: White LINK LED and Amber ACTIVE LED */
#define BUTTERFLY_NIC_LED_MODE 0x00
+
+/* SPI write protect, active low */
+#define WP_GPIO 6
+
#endif
diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c
index f4250cc247..f77c822f6c 100644
--- a/src/mainboard/google/link/chromeos.c
+++ b/src/mainboard/google/link/chromeos.c
@@ -6,6 +6,7 @@
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios)
{
@@ -26,12 +27,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
- return get_gpio(57);
+ return get_gpio(GPIO_SPI_WP);
}
static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(9, CROS_GPIO_DEVICE_NAME),
- CROS_GPIO_WP_AH(57, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)
diff --git a/src/mainboard/google/link/onboard.h b/src/mainboard/google/link/onboard.h
index 7e351e41f7..efcda92ef9 100644
--- a/src/mainboard/google/link/onboard.h
+++ b/src/mainboard/google/link/onboard.h
@@ -16,4 +16,8 @@
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a
#define BOARD_TOUCHSCREEN_IRQ 22
+#define GPIO_REC_MODE 9
+
+#define GPIO_SPI_WP 57
+
#endif
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c
index 77aa11a626..4781f7e622 100644
--- a/src/mainboard/google/parrot/chromeos.c
+++ b/src/mainboard/google/parrot/chromeos.c
@@ -8,10 +8,10 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
-#include <ec/compal/ene932/ec.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
-#include "ec.h"
+
+#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios)
{
@@ -20,7 +20,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
struct lb_gpio chromeos_gpios[] = {
/* Lid switch GPIO active high (open). */
- {15, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {GPIO_LID, ACTIVE_HIGH, get_lid_switch(), "lid"},
/* Power Button */
{101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"},
@@ -34,32 +34,27 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_lid_switch(void)
{
- return get_gpio(15);
+ return get_gpio(GPIO_LID);
}
int get_write_protect_state(void)
{
- return !get_gpio(70);
+ return !get_gpio(GPIO_SPI_WP);
}
int get_recovery_mode_switch(void)
{
- u8 gpio = !get_gpio(68);
- /* GPIO68, active low. For Servo support
- * Treat as active high and let the caller invert if needed. */
- printk(BIOS_DEBUG, "REC MODE GPIO 68: %x\n", gpio);
-
- return gpio;
+ return !get_gpio(GPIO_REC_MODE);
}
static int parrot_ec_running_ro(void)
{
- return !get_gpio(68);
+ return get_recovery_mode_switch();
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
- CROS_GPIO_WP_AL(70, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)
diff --git a/src/mainboard/google/parrot/onboard.h b/src/mainboard/google/parrot/onboard.h
index 9bece67886..d564c5695c 100644
--- a/src/mainboard/google/parrot/onboard.h
+++ b/src/mainboard/google/parrot/onboard.h
@@ -9,4 +9,13 @@
#define BOARD_TRACKPAD_IRQ_PVT 20
#define BOARD_TRACKPAD_WAKE_GPIO 0x1c
+#define GPIO_LID 15
+
+/* GPIO68, active low. For Servo support
+ * Treat as active high and let the caller invert if needed. */
+#define GPIO_REC_MODE 68
+
+
+#define GPIO_SPI_WP 70
+
#endif
diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c
index 5453583e87..0fa78c921f 100644
--- a/src/mainboard/google/slippy/chromeos.c
+++ b/src/mainboard/google/slippy/chromeos.c
@@ -6,6 +6,7 @@
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios)
{
@@ -19,12 +20,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
- return get_gpio(58);
+ return get_gpio(GPIO_SPI_WP);
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
- CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)
diff --git a/src/mainboard/google/slippy/onboard.h b/src/mainboard/google/slippy/onboard.h
index 6b7fdb281e..a1f30fda08 100644
--- a/src/mainboard/google/slippy/onboard.h
+++ b/src/mainboard/google/slippy/onboard.h
@@ -23,4 +23,7 @@
#define PEPPY_BOARD_VERSION_PROTO 0
#define PEPPY_BOARD_VERSION_EVT 1
+/* Write protect is active high */
+#define GPIO_SPI_WP 58
+
#endif
diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c
index e68093f592..6bbc640aea 100644
--- a/src/mainboard/google/stout/chromeos.c
+++ b/src/mainboard/google/stout/chromeos.c
@@ -12,6 +12,7 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include <ec/quanta/it8518/ec.h>
+#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios)
{
@@ -35,7 +36,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
- return !get_gpio(7);
+ return !get_gpio(GPIO_SPI_WP);
}
int get_lid_switch(void)
@@ -77,7 +78,7 @@ int get_recovery_mode_switch(void)
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
- CROS_GPIO_WP_AL(7, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)
diff --git a/src/mainboard/google/stout/onboard.h b/src/mainboard/google/stout/onboard.h
index a31dffd4cd..2f9b92d14b 100644
--- a/src/mainboard/google/stout/onboard.h
+++ b/src/mainboard/google/stout/onboard.h
@@ -11,4 +11,7 @@
#define XHCI_PREBOOT 0 // No PreOS boot support
#define XHCI_STREAMS 1 // Sure, lets have streams
+/* Write protect is active low */
+#define GPIO_SPI_WP 7
+
#endif
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index b6c41640ac..d4408f4d06 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -7,12 +7,13 @@
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
/* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */
- {69, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"},
+ {GPIO_REC_MODE, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"},
/* Hard code the lid switch GPIO to open. */
{-1, ACTIVE_HIGH, 1, "lid"},
@@ -32,18 +33,18 @@ int get_recovery_mode_switch(void)
* Recovery: GPIO69, Connected to J8E3, however the silkscreen says
* J8E2. The jump is active high.
*/
- return get_gpio(69);
+ return get_gpio(GPIO_REC_MODE);
}
int get_write_protect_state(void)
{
/* Write protect is active low, so invert it here */
- return !get_gpio(22);
+ return !get_gpio(GPIO_SPI_WP);
}
static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME),
- CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_REC_AH(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)
diff --git a/src/mainboard/intel/baskingridge/onboard.h b/src/mainboard/intel/baskingridge/onboard.h
new file mode 100644
index 0000000000..66812a55f0
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/onboard.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef BASKINGRIDGE_ONBOARD_H
+#define BASKINGRIDGE_ONBOARD_H
+
+/* Recovery: GPIO69, active high - SV_DETECT - J8E3 (silkscreen: J8E2) */
+#define GPIO_REC_MODE 69
+
+/* Write protect is active low */
+#define GPIO_SPI_WP 22
+
+#endif
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index 58732b11fb..2d0e2e1f44 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -7,12 +7,13 @@
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
/* Recovery: GPIO22 */
- {22, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"},
+ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"},
/* Hard code the lid switch GPIO to open. */
{-1, ACTIVE_HIGH, 1, "lid"},
@@ -29,18 +30,18 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_recovery_mode_switch(void)
{
/* Recovery: GPIO22, active low */
- return !get_gpio(22);
+ return !get_gpio(GPIO_REC_MODE);
}
int get_write_protect_state(void)
{
/* Write protect is active low, so invert it here */
- return !get_gpio(48);
+ return !get_gpio(GPIO_SPI_WP);
}
static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME),
- CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)
diff --git a/src/mainboard/intel/emeraldlake2/onboard.h b/src/mainboard/intel/emeraldlake2/onboard.h
new file mode 100644
index 0000000000..658ad83e19
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/onboard.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef EMERALDLAKE2_ONBOARD_H
+#define EMERALDLAKE2_ONBOARD_H
+
+/* Recovery: GPIO22, active low */
+#define GPIO_REC_MODE 22
+
+/* Write protect is active low */
+#define GPIO_SPI_WP 48
+
+#endif
diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c
index 3f80b68034..91ce9aed27 100644
--- a/src/mainboard/intel/strago/chromeos.c
+++ b/src/mainboard/intel/strago/chromeos.c
@@ -6,10 +6,7 @@
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
-#define WP_GPIO GP_E_22
-
-#define ACTIVE_LOW 0
-#define ACTIVE_HIGH 1
+#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios)
{
diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h
index bc2e7a278a..d8af569733 100644
--- a/src/mainboard/intel/strago/onboard.h
+++ b/src/mainboard/intel/strago/onboard.h
@@ -29,6 +29,9 @@
#define JACK_DETECT_GPIO_INDEX 95
/* SCI: Gpio index in N bank */
#define BOARD_SCI_GPIO_INDEX 15
+
+#define WP_GPIO GP_E_22
+
/* Trackpad: Gpio index in N bank */
#define BOARD_TRACKPAD_GPIO_INDEX 18
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 10:00:23 +0000