summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/xeon_sp/gnr/include/soc/iio.h90
-rw-r--r--src/soc/intel/xeon_sp/gnr/soc_iio.c17
2 files changed, 76 insertions, 31 deletions
diff --git a/src/soc/intel/xeon_sp/gnr/include/soc/iio.h b/src/soc/intel/xeon_sp/gnr/include/soc/iio.h
index cbc9113792..16095d1f3e 100644
--- a/src/soc/intel/xeon_sp/gnr/include/soc/iio.h
+++ b/src/soc/intel/xeon_sp/gnr/include/soc/iio.h
@@ -44,31 +44,39 @@ struct iio_port_config {
uint8_t vpp_mux_address; // SMBUS address of MUX used to access VPP
uint8_t vpp_mux_channel; // Channel of the MUX used to access VPP
- uint8_t slot_eip:1; // Electromechanical Interlock Present -
+ uint8_t npem_address; // SMBUS address of IO expander which provides NPEM
+ uint8_t npem_bank; // Port or bank on IoExpander which provides NPEM
+ uint8_t npem_mux_address; // SMBUS address of MUX used to access NPEM
+ uint8_t npem_mux_channel; // Channel of the MUX used to access NPEM
+
+ uint8_t slot_eip; // Electromechanical Interlock Present -
// Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
- uint8_t slot_hps:1; // Hot Plug surprise supported -
+ uint8_t slot_hps; // Hot Plug surprise supported -
// Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
- uint8_t slot_pind:1; // Power Indicator Present -
+ uint8_t slot_pind; // Power Indicator Present -
// Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
- uint8_t slot_aind:1; // Attention Inductor Present -
+ uint8_t slot_aind; // Attention Inductor Present -
// Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
- uint8_t slot_pctl:1; // Power Controller Present -
+ uint8_t slot_pctl; // Power Controller Present -
// Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
- uint8_t slot_abtn:1; // Attention Button Present -
+ uint8_t slot_abtn; // Attention Button Present -
// Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
- uint8_t slot_rsvd:2; // Reserved
- uint8_t vpp_enabled:1; // If VPP is supported on given port
- uint8_t vpp_exp_type:1; // IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE
+ uint8_t vpp_enabled; // If VPP is supported on given port
+ uint8_t vpp_exp_type; // IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE
// for values definitions)
+ uint8_t npem_supported; // If NPEM is supported on given port
- uint8_t slot_implemented:1;
- uint8_t reserved:4;
+ uint8_t slot_implemented;
+ uint8_t retimer_1_present;
+ uint8_t retimer_2_present;
+ uint8_t common_clock;
+ uint8_t sris;
- uint16_t hot_plug:1; // If hotplug is supported on slot connected to this port
- uint16_t mrl_sensor_present:1; // If MRL is present on slot connected to this port
- uint16_t slot_power_limit_scale:2; // Slot Power Scale for slot connected to this port
- uint16_t slot_power_limit_value:12; // Slot Power Value for slot connected to this port
+ uint16_t hot_plug; // If hotplug is supported on slot connected to this port
+ uint16_t mrl_sensor_present; // If MRL is present on slot connected to this port
+ uint16_t slot_power_limit_scale; // Slot Power Scale for slot connected to this port
+ uint16_t slot_power_limit_value; // Slot Power Value for slot connected to this port
uint16_t physical_slot_number; // Slot number for slot connected to this port
};
@@ -77,8 +85,8 @@ struct iio_pe_config {
uint8_t socket;
IIO_PACKAGE_PE pe;
IIO_BIFURCATION bifurcation;
- uint8_t cxl_support:1;
- uint8_t reserved:7;
+ uint8_t cxl_support;
+ uint8_t reserved;
struct iio_port_config port_config[MAX_IIO_PORTS_PER_STACK];
};
@@ -102,11 +110,12 @@ struct iio_pe_config {
.reserved = 0,\
.port_config =
-/* TODO: to update rsv1 - rsv5 after SoC launch */
#define _IIO_PORT_CFG_STRUCT(vppen, vppex, vaddr, vport, vmuxa, vmuxc,\
- slteip, slthps, sltpind, sltaind, sltpctl, sltabtn, hotp, mrlsp,\
- sltimpl, sltpls, sltplv, psn,\
- rsv1, rsv2, rsv3, rsv4, rsv5) {\
+ slteip, slthps, sltpind, sltaind, sltpctl, sltabtn,\
+ sltimpl, hotp, mrlsp, sltpls, sltplv, psn,\
+ retimer1, retimer2, comclk, dsris,\
+ npmspt, npaddr, npb, npma, npmc\
+ ) {\
.vpp_enabled = (vppen),\
.vpp_exp_type = (vppex),\
.vpp_address = (vaddr),\
@@ -119,32 +128,57 @@ struct iio_pe_config {
.slot_aind = (sltaind),\
.slot_pctl = (sltpctl),\
.slot_abtn = (sltabtn),\
- .slot_rsvd = 0,\
.slot_implemented = (sltimpl),\
- .reserved = 0,\
+ .retimer_1_present = (retimer1),\
+ .retimer_2_present = (retimer2),\
+ .common_clock = (comclk),\
+ .sris = (dsris),\
.hot_plug = (hotp),\
.mrl_sensor_present = (mrlsp),\
.slot_power_limit_scale = (sltpls),\
.slot_power_limit_value = (sltplv),\
- .physical_slot_number = (psn)\
+ .physical_slot_number = (psn),\
+ .npem_supported = (npmspt),\
+ .npem_address = (npaddr),\
+ .npem_bank = (npb),\
+ .npem_mux_address = (npma),\
+ .npem_mux_channel = (npmc),\
}
#define _IIO_PORT_CFG_STRUCT_DISABLED \
- _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
- 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0)
+ _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
+ 0x0, 0x0, 0x0, 0x0,\
+ 0x0, 0x0, 0x0, 0x0, 0x0)
#define _IIO_PORT_CFG_STRUCT_X8 _IIO_PORT_CFG_STRUCT
#define _IIO_PORT_CFG_STRUCT_X4 _IIO_PORT_CFG_STRUCT
#define _IIO_PORT_CFG_STRUCT_X2 _IIO_PORT_CFG_STRUCT
#define _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn)\
- _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
- 0x0, 0x0, 0x0, 0x1, sltpls, sltplv, psn, 0x0, 0x0, 0x0, 0x0, 0x0)
+ _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
+ 0x1, 0x0, 0x0, sltpls, sltplv, psn,\
+ 0x0, 0x0, 0x1, 0x0,\
+ 0x0, 0x0, 0x0, 0x0, 0x0)
#define _IIO_PORT_CFG_STRUCT_BASIC_X8 _IIO_PORT_CFG_STRUCT_BASIC
#define _IIO_PORT_CFG_STRUCT_BASIC_X4 _IIO_PORT_CFG_STRUCT_BASIC
#define _IIO_PORT_CFG_STRUCT_BASIC_X2 _IIO_PORT_CFG_STRUCT_BASIC
+#define _IIO_PE_CFG_DISABLED(socket, pe) {\
+ _IIO_PE_CFG_STRUCT(socket, pe, IIO_BIFURCATE_AUTO, PE_TYPE_PCIE) {\
+ _IIO_PORT_CFG_STRUCT_DISABLED,\
+ _IIO_PORT_CFG_STRUCT_DISABLED,\
+ _IIO_PORT_CFG_STRUCT_DISABLED,\
+ _IIO_PORT_CFG_STRUCT_DISABLED,\
+ _IIO_PORT_CFG_STRUCT_DISABLED,\
+ _IIO_PORT_CFG_STRUCT_DISABLED,\
+ _IIO_PORT_CFG_STRUCT_DISABLED,\
+ _IIO_PORT_CFG_STRUCT_DISABLED,\
+ }}
+
void soc_config_iio_pe_ports(FSPM_UPD *mupd, const struct iio_pe_config *config_table,
unsigned int num_entries);
diff --git a/src/soc/intel/xeon_sp/gnr/soc_iio.c b/src/soc/intel/xeon_sp/gnr/soc_iio.c
index 230d407068..056168986e 100644
--- a/src/soc/intel/xeon_sp/gnr/soc_iio.c
+++ b/src/soc/intel/xeon_sp/gnr/soc_iio.c
@@ -36,11 +36,21 @@ void soc_config_iio_pe_ports(FSPM_UPD *mupd, const struct iio_pe_config *config_
upd_pe_config->Bifurcation = board_pe_config->bifurcation;
upd_pe_config->CxlSupportInUba = board_pe_config->cxl_support;
+ upd_port_config->VppEnabled = board_port_config->vpp_enabled;
+ upd_port_config->VppExpType = board_port_config->vpp_exp_type;
+
upd_port_config->Vpp.Address = board_port_config->vpp_address;
upd_port_config->Vpp.Port = board_port_config->vpp_port;
upd_port_config->Vpp.MuxAddress = board_port_config->vpp_mux_address;
upd_port_config->Vpp.MuxChannel = board_port_config->vpp_mux_channel;
+ upd_port_config->NpemSupported = board_port_config->npem_supported;
+
+ upd_port_config->Npem.Address = board_port_config->npem_address;
+ upd_port_config->Npem.Bank = board_port_config->npem_bank;
+ upd_port_config->Npem.MuxAddress = board_port_config->npem_mux_address;
+ upd_port_config->Npem.MuxChannel = board_port_config->npem_mux_channel;
+
upd_port_config->Slot.Eip = board_port_config->slot_eip;
upd_port_config->Slot.HotPlugSurprise = board_port_config->slot_hps;
upd_port_config->Slot.PowerInd = board_port_config->slot_pind;
@@ -48,15 +58,16 @@ void soc_config_iio_pe_ports(FSPM_UPD *mupd, const struct iio_pe_config *config_
upd_port_config->Slot.PowerCtrl = board_port_config->slot_pctl;
upd_port_config->Slot.AttentionBtn = board_port_config->slot_abtn;
- upd_port_config->VppEnabled = board_port_config->vpp_enabled;
- upd_port_config->VppExpType = board_port_config->vpp_exp_type;
-
upd_port_config->SlotImplemented = board_port_config->slot_implemented;
upd_port_config->HotPlug = board_port_config->hot_plug;
upd_port_config->MrlSensorPresent = board_port_config->mrl_sensor_present;
upd_port_config->SlotPowerLimitScale = board_port_config->slot_power_limit_scale;
upd_port_config->SlotPowerLimitValue = board_port_config->slot_power_limit_value;
upd_port_config->PhysicalSlotNumber = board_port_config->physical_slot_number;
+ upd_port_config->Retimer1Present = board_port_config->retimer_1_present;
+ upd_port_config->Retimer2Present = board_port_config->retimer_2_present;
+ upd_port_config->CommonClock = board_port_config->common_clock;
+ upd_port_config->SRIS = board_port_config->sris;
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-19 04:27:20 +0000