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-rw-r--r--src/soc/intel/pantherlake/chip.h2
-rw-r--r--src/soc/intel/pantherlake/romstage/fsp_params.c3
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index b59ce5e8e6..5846037c95 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -512,6 +512,8 @@ struct soc_intel_pantherlake_config {
*/
uint8_t slow_slew_rate_config[NUM_VR_DOMAINS];
+ uint16_t max_dram_speed_mts;
+
};
typedef struct soc_intel_pantherlake_config config_t;
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index b105d3d58a..e6ed19ec85 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -74,6 +74,9 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3;
}
+ if (config->max_dram_speed_mts)
+ m_cfg->DdrFreqLimit = config->max_dram_speed_mts;
+
m_cfg->RMT = config->rmt;
m_cfg->MrcFastBoot = 1;
}