diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/haswell/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/cache_as_ram.inc | 11 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/haswell.h | 5 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 53 | ||||
| -rw-r--r-- | src/mainboard/intel/baskingridge/romstage.c | 8 | ||||
| -rw-r--r-- | src/mainboard/intel/wtm1/romstage.c | 7 | ||||
| -rw-r--r-- | src/mainboard/intel/wtm2/romstage.c | 7 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/Kconfig | 19 |
8 files changed, 89 insertions, 22 deletions
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 67b095433e..b2116f2dfe 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += haswell_init.c subdirs-y += ../../x86/name +romstage-y += romstage.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index f5ee82e2d2..72b49589d4 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -24,7 +24,11 @@ #include <cpu/x86/post_code.h> #include <cbmem.h> -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +/* The full cache-as-ram size includes the cache-as-ram portion from coreboot + * and the space used by the reference code. These 2 values combined should + * be a power of 2 because the MTRR setup assumes that. */ +#define CACHE_AS_RAM_SIZE \ + (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE /* Cache 4GB - MRC_SIZE_KB for MRC */ @@ -166,9 +170,8 @@ clear_mtrrs: andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - /* Set up the stack pointer below MRC variable space. */ - movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \ - CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4), %eax + /* Setup the stack. */ + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp /* Restore the BIST result. */ diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index cb85078db4..8d91dbaf02 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -101,6 +101,11 @@ #define PSS_LATENCY_BUSMASTER 10 #ifndef __ROMCC__ + +#if defined(__PRE_RAM__) +void romstage_main(unsigned long bist); +#endif + #ifdef __SMM__ /* Lock MSRs */ void intel_cpu_haswell_finalize_smm(void); diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c new file mode 100644 index 0000000000..f954b91dca --- /dev/null +++ b/src/cpu/intel/haswell/romstage.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cbmem.h> +#include <console/console.h> + +/* Mainboard needs to supply this symbol. */ +extern void romstage_main(unsigned long bist); + +void main(unsigned long bist) +{ + int i; + const int num_guards = 4; + const u32 stack_guard = 0xdeadbeef; + u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - + CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE); + + printk(BIOS_DEBUG, "Setting up stack guards.\n"); + for (i = 0; i < num_guards; i++) + stack_base[i] = stack_guard; + + romstage_main(bist); + + /* Check the stack. */ + for (i = 0; i < num_guards; i++) { + if (stack_base[i] == stack_guard) + continue; + printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); + } + +#if CONFIG_CONSOLE_CBMEM + /* Keep this the last thing this function does. */ + cbmemc_reinit(); +#endif +} diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index d47fbf13a2..45316f62b9 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -30,6 +30,7 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> +#include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" #include "northbridge/intel/haswell/raminit.h" #include "southbridge/intel/lynxpoint/pch.h" @@ -82,7 +83,7 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void main(unsigned long bist) +void romstage_main(unsigned long bist) { int boot_mode = 0; int wake_from_s3; @@ -236,8 +237,5 @@ void main(unsigned long bist) timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); #endif -#if CONFIG_CONSOLE_CBMEM - /* Keep this the last thing this function does. */ - cbmemc_reinit(); -#endif } + diff --git a/src/mainboard/intel/wtm1/romstage.c b/src/mainboard/intel/wtm1/romstage.c index 0190964b26..c80c721eaf 100644 --- a/src/mainboard/intel/wtm1/romstage.c +++ b/src/mainboard/intel/wtm1/romstage.c @@ -30,6 +30,7 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> +#include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" #include "northbridge/intel/haswell/raminit.h" #include "southbridge/intel/lynxpoint/me.h" @@ -87,7 +88,7 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void main(unsigned long bist) +void romstage_main(unsigned long bist) { int boot_mode = 0; int wake_from_s3; @@ -241,8 +242,4 @@ void main(unsigned long bist) timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); #endif -#if CONFIG_CONSOLE_CBMEM - /* Keep this the last thing this function does. */ - cbmemc_reinit(); -#endif } diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 100195b485..a4a42d3f70 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -30,6 +30,7 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> +#include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" #include "northbridge/intel/haswell/raminit.h" #include "southbridge/intel/lynxpoint/me.h" @@ -87,7 +88,7 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void main(unsigned long bist) +void romstage_main(unsigned long bist) { int boot_mode = 0; int wake_from_s3; @@ -241,8 +242,4 @@ void main(unsigned long bist) timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); #endif -#if CONFIG_CONSOLE_CBMEM - /* Keep this the last thing this function does. */ - cbmemc_reinit(); -#endif } diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index a7f1f9be57..f68978040f 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -59,15 +59,28 @@ config MRC_CACHE_SIZE config DCACHE_RAM_BASE hex - default 0xff7e0000 + default 0xff7c0000 config DCACHE_RAM_SIZE hex - default 0x20000 + default 0x10000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE + must add up to a power of 2. config DCACHE_RAM_MRC_VAR_SIZE hex - default 0x4000 + default 0x30000 + help + The amount of cache-as-ram region required by the reference code. + +config DCACHE_RAM_ROMSTAGE_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage from the data cache + during pre-ram rom stage execution. config HAVE_MRC bool "Add a System Agent binary" |