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-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index ccde132176..6a826c0bd2 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -255,6 +255,15 @@ chip soc/intel/tigerlake
# Enable DPTF
register "dptf_enable" = "1"
+ # Enable External Bypass
+ register "external_bypass" = "1"
+
+ # Enable External Clk Gate
+ register "external_clk_gated" = "1"
+
+ # Enable External Phy Gate
+ register "external_phy_gated" = "1"
+
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 38,