4 files changed, 115 insertions, 0 deletions

diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig
index 9dd8a5e7f3..d2dd7ce014 100644
--- a/src/mainboard/intel/Kconfig
+++ b/src/mainboard/intel/Kconfig
@@ -3,6 +3,8 @@ if VENDOR_INTEL
 choice
 	prompt "Mainboard model"
 
+config BOARD_INTEL_BAKERSPORT_FSP
+	bool "Bakersport FSP-based CRB"
 config BOARD_INTEL_BAYLEYBAY_FSP
 	bool "Bayley Bay FSP-based CRB"
 config BOARD_INTEL_COUGAR_CANYON2
@@ -34,6 +36,7 @@ config BOARD_INTEL_WTM2
 
 endchoice
 
+source "src/mainboard/intel/bakersport_fsp/Kconfig"
 source "src/mainboard/intel/bayleybay_fsp/Kconfig"
 source "src/mainboard/intel/cougar_canyon2/Kconfig"
 source "src/mainboard/intel/d810e2cb/Kconfig"
diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig
new file mode 100644
index 0000000000..043e98a41c
--- /dev/null
+++ b/src/mainboard/intel/bakersport_fsp/Kconfig
@@ -0,0 +1,103 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_INTEL_BAKERSPORT_FSP
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select SOC_INTEL_FSP_BAYTRAIL
+	select BOARD_ROMSIZE_KB_2048
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select OVERRIDE_MRC_CACHE_LOC
+	select POST_IO
+	select INCLUDE_MICROCODE_IN_BUILD if FSP_PACKAGE_DEFAULT
+	select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
+	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
+	select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT
+	select TSC_MONOTONIC_TIMER
+
+config MAINBOARD_DIR
+	string
+	default "intel/bayleybay_fsp"
+
+config INCLUDE_ME
+	bool
+	default n
+
+config LOCK_MANAGEMENT_ENGINE
+	bool
+	default n
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Bakersport CRB"
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 16
+
+config CACHE_ROM_SIZE_OVERRIDE
+	hex
+	default 0x800000
+
+config FSP_FILE
+	string
+	default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP
+
+config MRC_CACHE_LOC_OVERRIDE
+	hex
+	default 0xfff80000
+	depends on ENABLE_FSP_FAST_BOOT
+
+config CBFS_SIZE
+	hex
+	default 0x00200000
+
+config DRIVERS_PS2_KEYBOARD
+	bool
+	default n
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ENABLE_FSP_FAST_BOOT
+	bool
+	depends on HAVE_FSP_BIN
+	default y
+
+config VIRTUAL_ROM_SIZE
+	hex
+	depends on ENABLE_FSP_FAST_BOOT
+	default 0x800000
+
+config FSP_PACKAGE_DEFAULT
+	bool "Configure defaults for the Intel FSP package"
+	default n
+
+config VGA_BIOS
+	bool
+	default y if FSP_PACKAGE_DEFAULT
+
+endif # BOARD_INTEL_BAKERSPORT_FSP
diff --git a/src/mainboard/intel/bakersport_fsp/board_info.txt b/src/mainboard/intel/bakersport_fsp/board_info.txt
new file mode 100644
index 0000000000..8527d4128d
--- /dev/null
+++ b/src/mainboard/intel/bakersport_fsp/board_info.txt
@@ -0,0 +1,4 @@
+Board name: Bakersport
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c
index 34199bd2b8..ef848faa23 100644
--- a/src/mainboard/intel/bayleybay_fsp/romstage.c
+++ b/src/mainboard/intel/bayleybay_fsp/romstage.c
@@ -173,4 +173,9 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
 
 	/* Initialize the Azalia Verb Tables to mainboard specific version */
 	UpdData->AzaliaConfigPtr  = (UINT32)&mainboard_AzaliaConfig;
+
+	/* Disable 2nd DIMM on Bakersport*/
+#if IS_ENABLED(BOARD_INTEL_BAKERSPORT_FSP)
+	UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */
+#endif
 }