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-rw-r--r--src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl196
1 files changed, 98 insertions, 98 deletions
diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl
index 2f5328f100..9926367536 100644
--- a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl
+++ b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl
@@ -7,225 +7,225 @@
*/
#define GEN_PCIE_LEGACY_IRQ() \
- Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, \
- Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, \
- Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 }, \
- Package (0x04) { 0x0003FFFF, 0x00, LNKA, 0x00 }
+ Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \
+ Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, \
+ Package () { 0x0002FFFF, 0x00, LNKA, 0x00 }, \
+ Package () { 0x0003FFFF, 0x00, LNKA, 0x00 }
#define GEN_UNCORE_LEGACY_IRQ(dev) \
- Package (0x04) { ##dev, 0x00, LNKA, 0x00 }, \
- Package (0x04) { ##dev, 0x01, LNKB, 0x00 }, \
- Package (0x04) { ##dev, 0x02, LNKC, 0x00 }, \
- Package (0x04) { ##dev, 0x03, LNKD, 0x00 }
+ Package () { ##dev, 0x00, LNKA, 0x00 }, \
+ Package () { ##dev, 0x01, LNKB, 0x00 }, \
+ Package () { ##dev, 0x02, LNKC, 0x00 }, \
+ Package () { ##dev, 0x03, LNKD, 0x00 }
#define GEN_PCIE_IOAPIC_IRQ(irq) \
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, ##irq }, \
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, ##irq }, \
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, ##irq }, \
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, ##irq }
+ Package () { 0x0000FFFF, 0x00, 0x00, ##irq }, \
+ Package () { 0x0001FFFF, 0x00, 0x00, ##irq }, \
+ Package () { 0x0002FFFF, 0x00, 0x00, ##irq }, \
+ Package () { 0x0003FFFF, 0x00, 0x00, ##irq }
#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \
- Package (0x04) { ##dev, 0x00, 0x00, ##irq1 }, \
- Package (0x04) { ##dev, 0x01, 0x00, ##irq2 }, \
- Package (0x04) { ##dev, 0x02, 0x00, ##irq3 }, \
- Package (0x04) { ##dev, 0x03, 0x00, ##irq4 }
+ Package () { ##dev, 0x00, 0x00, ##irq1 }, \
+ Package () { ##dev, 0x01, 0x00, ##irq2 }, \
+ Package () { ##dev, 0x02, 0x00, ##irq3 }, \
+ Package () { ##dev, 0x03, 0x00, ##irq4 }
// Socket 0, IIOStack 0 device legacy interrupt routing
Name (PR00, Package (0x28)
{
// [DMI0]: Legacy PCI Express Port 0
- Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0000FFFF, 0x00, LNKA, 0x00 },
// [CB0A]: CBDMA
// [CB0E]: CBDMA
- Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0004FFFF, 0x00, LNKA, 0x00 },
// [CB0B]: CBDMA
// [CB0F]: CBDMA
- Package (0x04) { 0x0004FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0004FFFF, 0x01, LNKB, 0x00 },
// [CB0C]: CBDMA
// [CB0G]: CBDMA
- Package (0x04) { 0x0004FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0004FFFF, 0x02, LNKC, 0x00 },
// [CB0D]: CBDMA
// [CB0H]: CBDMA
- Package (0x04) { 0x0004FFFF, 0x03, LNKD, 0x00 },
+ Package () { 0x0004FFFF, 0x03, LNKD, 0x00 },
// Uncore 0 UBOX Device
- Package (0x04) { 0x0008FFFF, 0x00, LNKA, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x01, LNKB, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x02, LNKC, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x03, LNKD, 0x00 },
+ Package () { 0x0008FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0008FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0008FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0008FFFF, 0x03, LNKD, 0x00 },
// [DISP]: Display Controller
- Package (0x04) { 0x000FFFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x000FFFFF, 0x00, LNKA, 0x00 },
// [IHC1]: HECI #1
// [IHC3]: HECI #3
- Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0010FFFF, 0x00, LNKA, 0x00 },
// [IHC2]: HECI #2
- Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0010FFFF, 0x01, LNKB, 0x00 },
// [IIDR]: IDE-Redirection (IDE-R)
- Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0010FFFF, 0x02, LNKC, 0x00 },
// [IMKT]: Keyboard and Text (KT) Redirection
- Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 },
+ Package () { 0x0010FFFF, 0x03, LNKD, 0x00 },
// [SAT2]: sSATA Host controller 2 on PCH
- Package (0x04) { 0x0011FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0011FFFF, 0x00, LNKA, 0x00 },
// // [XHCI]: xHCI controller 1 on PCH
- Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0014FFFF, 0x00, LNKA, 0x00 },
// [OTG0]: USB Device Controller (OTG) on PCH
- Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0014FFFF, 0x01, LNKB, 0x00 },
// [TERM]: Thermal Subsystem on PCH
- Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0014FFFF, 0x02, LNKC, 0x00 },
// [CAMR]: Camera IO Host Controller on PCH
- Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 },
+ Package () { 0x0014FFFF, 0x03, LNKD, 0x00 },
// [HEC1]: HECI #1 on PCH
// [HEC3]: HECI #3 on PCH
- Package (0x04) { 0x0016FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0016FFFF, 0x00, LNKA, 0x00 },
// [HEC2]: HECI #2 on PCH
- Package (0x04) { 0x0016FFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x0016FFFF, 0x01, LNKB, 0x00 },
// [IDER]: ME IDE redirect on PCH
- Package (0x04) { 0x0016FFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x0016FFFF, 0x02, LNKC, 0x00 },
// [MEKT]: MEKT on PCH
- Package (0x04) { 0x0016FFFF, 0x03, LNKD, 0x00 },
+ Package () { 0x0016FFFF, 0x03, LNKD, 0x00 },
// [SAT1]: SATA controller 1 on PCH
- Package (0x04) { 0x0017FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0017FFFF, 0x00, LNKA, 0x00 },
// [NAN1]: NAND Cycle Router on PCH
- Package (0x04) { 0x0018FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0018FFFF, 0x00, LNKA, 0x00 },
// [RP17]: PCIE PCH Root Port #17
- Package (0x04) { 0x001BFFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x001BFFFF, 0x00, LNKA, 0x00 },
// [RP18]: PCIE PCH Root Port #18
- Package (0x04) { 0x001BFFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x001BFFFF, 0x01, LNKB, 0x00 },
// [RP19]: PCIE PCH Root Port #19
- Package (0x04) { 0x001BFFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x001BFFFF, 0x02, LNKC, 0x00 },
// [RP20]: PCIE PCH Root Port #20
- Package (0x04) { 0x001BFFFF, 0x03, LNKD, 0x00 },
+ Package () { 0x001BFFFF, 0x03, LNKD, 0x00 },
// [RP01]: PCIE PCH Root Port #1
// [RP05]: PCIE PCH Root Port #5
- Package (0x04) { 0x001CFFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x001CFFFF, 0x00, LNKA, 0x00 },
// [RP02]: PCIE PCH Root Port #2
// [RP06]: PCIE PCH Root Port #6
- Package (0x04) { 0x001CFFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x001CFFFF, 0x01, LNKB, 0x00 },
// [RP03]: PCIE PCH Root Port #3
// [RP07]: PCIE PCH Root Port #7
- Package (0x04) { 0x001CFFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x001CFFFF, 0x02, LNKC, 0x00 },
// [RP04]: PCIE PCH Root Port #4
// [RP08]: PCIE PCH Root Port #8
- Package (0x04) { 0x001CFFFF, 0x03, LNKD, 0x00 },
+ Package () { 0x001CFFFF, 0x03, LNKD, 0x00 },
// [RP09]: PCIE PCH Root Port #9
// [RP13]: PCIE PCH Root Port #13
- Package (0x04) { 0x001DFFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x001DFFFF, 0x00, LNKA, 0x00 },
// [RP10]: PCIE PCH Root Port #10
// [RP14]: PCIE PCH Root Port #14
- Package (0x04) { 0x001DFFFF, 0x01, LNKB, 0x00 },
+ Package () { 0x001DFFFF, 0x01, LNKB, 0x00 },
// [RP11]: PCIE PCH Root Port #11
// [RP15]: PCIE PCH Root Port #15
- Package (0x04) { 0x001DFFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x001DFFFF, 0x02, LNKC, 0x00 },
// [RP12]: PCIE PCH Root Port #12
// [RP16]: PCIE PCH Root Port #16
- Package (0x04) { 0x001DFFFF, 0x03, LNKD, 0x00 },
+ Package () { 0x001DFFFF, 0x03, LNKD, 0x00 },
// [UAR0]: UART #0 on PCH
- Package (0x04) { 0x001EFFFF, 0x02, LNKC, 0x00 },
+ Package () { 0x001EFFFF, 0x02, LNKC, 0x00 },
// [UAR1]: UART #1 on PCH
- Package (0x04) { 0x001EFFFF, 0x03, LNKD, 0x00 },
+ Package () { 0x001EFFFF, 0x03, LNKD, 0x00 },
// [CAVS]: HD Audio Subsystem Controller on PCH
// [SMBS]: SMBus controller on PCH
// [GBE1]: GbE Controller on PCH
// [NTPK]: Northpeak Controller on PCH
- Package (0x04) { 0x001FFFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x001FFFFF, 0x00, LNKA, 0x00 },
})
// Socket 0, IIOStack 0 device IOAPIC interrupt routing
Name (AR00, Package (0x28)
{
// [DMI0]: Legacy PCI Express Port 0
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1F },
+ Package () { 0x0000FFFF, 0x00, 0x00, 0x1F },
// [CB0A]: CB3DMA
// [CB0E]: CB3DMA
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A },
+ Package () { 0x0004FFFF, 0x00, 0x00, 0x1A },
// [CB0B]: CB3DMA
// [CB0F]: CB3DMA
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
+ Package () { 0x0004FFFF, 0x01, 0x00, 0x1B },
// [CB0C]: CB3DMA
// [CB0G]: CB3DMA
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A },
+ Package () { 0x0004FFFF, 0x02, 0x00, 0x1A },
// [CB0D]: CB3DMA
// [CB0H]: CB3DMA
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B },
+ Package () { 0x0004FFFF, 0x03, 0x00, 0x1B },
// [UBX0]: Uncore 0 UBOX Device
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 },
- Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x1C },
- Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1D },
- Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1E },
+ Package () { 0x0008FFFF, 0x00, 0x00, 0x18 },
+ Package () { 0x0008FFFF, 0x01, 0x00, 0x1C },
+ Package () { 0x0008FFFF, 0x02, 0x00, 0x1D },
+ Package () { 0x0008FFFF, 0x03, 0x00, 0x1E },
// [DISP]: Display Controller
- Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x000FFFFF, 0x00, 0x00, 0x10 },
// [IHC1]: HECI #1
// [IHC3]: HECI #3
- Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x0010FFFF, 0x00, 0x00, 0x10 },
// [IHC2]: HECI #2
- Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x0010FFFF, 0x01, 0x00, 0x11 },
// [IIDR]: IDE-Redirection (IDE-R)
- Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x0010FFFF, 0x02, 0x00, 0x12 },
// [IMKT]: Keyboard and Text (KT) Redirection
- Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x13 },
+ Package () { 0x0010FFFF, 0x03, 0x00, 0x13 },
// [SAT2]: sSATA Host controller 2 on PCH
- Package (0x04) { 0x0011FFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x0011FFFF, 0x00, 0x00, 0x10 },
// [XHCI]: xHCI controller 1 on PCH
- Package (0x04) { 0x0014FFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x0014FFFF, 0x00, 0x00, 0x10 },
// [OTG0]: USB Device Controller (OTG) on PCH
- Package (0x04) { 0x0014FFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x0014FFFF, 0x01, 0x00, 0x11 },
// [TERM]: Thermal Subsystem on PCH
- Package (0x04) { 0x0014FFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x0014FFFF, 0x02, 0x00, 0x12 },
// [CAMR]: Camera IO Host Controller on PCH
- Package (0x04) { 0x0014FFFF, 0x03, 0x00, 0x13 },
+ Package () { 0x0014FFFF, 0x03, 0x00, 0x13 },
// [HEC1]: HECI #1 on PCH
// [HEC3]: HECI #3 on PCH
- Package (0x04) { 0x0016FFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x0016FFFF, 0x00, 0x00, 0x10 },
// [HEC2]: HECI #2 on PCH
- Package (0x04) { 0x0016FFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x0016FFFF, 0x01, 0x00, 0x11 },
// [IDER]: ME IDE redirect on PCH
- Package (0x04) { 0x0016FFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x0016FFFF, 0x02, 0x00, 0x12 },
// [MEKT]: MEKT on PCH
- Package (0x04) { 0x0016FFFF, 0x03, 0x00, 0x13 },
+ Package () { 0x0016FFFF, 0x03, 0x00, 0x13 },
// [SAT1]: SATA controller 1 on PCH
- Package (0x04) { 0x0017FFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x0017FFFF, 0x00, 0x00, 0x10 },
// [NAN1]: NAND Cycle Router on PCH
- Package (0x04) { 0x0018FFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x0018FFFF, 0x00, 0x00, 0x10 },
// [RP17]: PCIE PCH Root Port #17
- Package (0x04) { 0x001BFFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x001BFFFF, 0x00, 0x00, 0x10 },
// [RP18]: PCIE PCH Root Port #18
- Package (0x04) { 0x001BFFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x001BFFFF, 0x01, 0x00, 0x11 },
// [RP19]: PCIE PCH Root Port #19
- Package (0x04) { 0x001BFFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x001BFFFF, 0x02, 0x00, 0x12 },
// [RP20]: PCIE PCH Root Port #20
- Package (0x04) { 0x001BFFFF, 0x03, 0x00, 0x13 },
+ Package () { 0x001BFFFF, 0x03, 0x00, 0x13 },
// [RP01]: PCIE PCH Root Port #1
// [RP05]: PCIE PCH Root Port #5
- Package (0x04) { 0x001CFFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x001CFFFF, 0x00, 0x00, 0x10 },
// [RP02]: PCIE PCH Root Port #2
// [RP06]: PCIE PCH Root Port #6
- Package (0x04) { 0x001CFFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x001CFFFF, 0x01, 0x00, 0x11 },
// [RP03]: PCIE PCH Root Port #3
// [RP07]: PCIE PCH Root Port #7
- Package (0x04) { 0x001CFFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x001CFFFF, 0x02, 0x00, 0x12 },
// [RP04]: PCIE PCH Root Port #4
// [RP08]: PCIE PCH Root Port #8
- Package (0x04) { 0x001CFFFF, 0x03, 0x00, 0x13 },
+ Package () { 0x001CFFFF, 0x03, 0x00, 0x13 },
// [RP09]: PCIE PCH Root Port #9
// [RP13]: PCIE PCH Root Port #13
- Package (0x04) { 0x001DFFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x001DFFFF, 0x00, 0x00, 0x10 },
// [RP10]: PCIE PCH Root Port #10
// [RP14]: PCIE PCH Root Port #14
- Package (0x04) { 0x001DFFFF, 0x01, 0x00, 0x11 },
+ Package () { 0x001DFFFF, 0x01, 0x00, 0x11 },
// [RP11]: PCIE PCH Root Port #11
// [RP15]: PCIE PCH Root Port #15
- Package (0x04) { 0x001DFFFF, 0x02, 0x00, 0x12 },
+ Package () { 0x001DFFFF, 0x02, 0x00, 0x12 },
// [RP12]: PCIE PCH Root Port #12
// [RP16]: PCIE PCH Root Port #16
- Package (0x04) { 0x001DFFFF, 0x03, 0x00, 0x13 },
+ Package () { 0x001DFFFF, 0x03, 0x00, 0x13 },
// [UAR0]: UART #0 on PCH
- Package (0x04) { 0x001EFFFF, 0x02, 0x00, 0x16 },
+ Package () { 0x001EFFFF, 0x02, 0x00, 0x16 },
// [UAR1]: UART #1 on PCH
- Package (0x04) { 0x001EFFFF, 0x03, 0x00, 0x17 },
+ Package () { 0x001EFFFF, 0x03, 0x00, 0x17 },
// [CAVS]: HD Audio Subsystem Controller on PCH
// [SMBS]: SMBus controller on PCH
// [GBE1]: GbE Controller on PCH
// [NTPK]: Northpeak Controller on PCH
- Package (0x04) { 0x001FFFFF, 0x00, 0x00, 0x10 },
+ Package () { 0x001FFFFF, 0x00, 0x00, 0x10 },
})
// Socket 0, IIOStack 1 device legacy interrupt routing
@@ -406,7 +406,7 @@ Name (AR28, Package (0x20)
Name (PR40, Package (0x09)
{
// DMI
- Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 },
+ Package () { 0x0000FFFF, 0x00, LNKA, 0x00 },
// CBDMA
GEN_UNCORE_LEGACY_IRQ(0x0004FFFF),
@@ -419,7 +419,7 @@ Name (PR40, Package (0x09)
Name (AR40, Package (0x09)
{
// DMI
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x4F },
+ Package () { 0x0000FFFF, 0x00, 0x00, 0x4F },
// CBDMA
GEN_UNCORE_IOAPIC_IRQ(0x0004FFFF, 0x4A, 0x4B, 0x4A, 0x4B),
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 03:30:48 +0000