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-rw-r--r--src/soc/intel/alderlake/acpi/xhci.asl18
-rw-r--r--src/soc/intel/cannonlake/acpi/xhci.asl17
-rw-r--r--src/soc/intel/common/block/include/intelblocks/xhci.h16
-rw-r--r--src/soc/intel/skylake/acpi/xhci.asl16
4 files changed, 24 insertions, 43 deletions
diff --git a/src/soc/intel/alderlake/acpi/xhci.asl b/src/soc/intel/alderlake/acpi/xhci.asl
index 465f0aa0b1..e4001fe8c2 100644
--- a/src/soc/intel/alderlake/acpi/xhci.asl
+++ b/src/soc/intel/alderlake/acpi/xhci.asl
@@ -1,18 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <intelblocks/xhci.h>
#include <soc/gpe.h>
-#define PORTSCN_OFFSET 0x480
-#define PORTSCXUSB3_OFFSET 0x540
-
-#define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000
-/*
- * And port status/control reg with RO and RWS bits
- * RO bits: 0, 2:3, 10:13, 24, 28:30
- * RWS bits: 5:9, 14:16, 25:27
- */
-#define RO_BITS_OFF_MASK ~0x80FE0012
-
/*
* USB Port Wake Enable (UPWE) on usb attach/detach
* Arg0 - Port Number
@@ -30,10 +20,8 @@ Method (UPWE, 3, Serialized)
PSCT, 32,
}
Local0 = PSCT
-
- Local0 &= RO_BITS_OFF_MASK
- /* Set WCE and WDE bits */
- Local0 |= WAKE_ON_CONNECT_DISCONNECT_ENABLE
+ Local0 &= PORTSCN_BITS_OFF_MASK
+ Local0 |= PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE
PSCT = Local0
}
diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl
index bc4574d222..0f8f51fe20 100644
--- a/src/soc/intel/cannonlake/acpi/xhci.asl
+++ b/src/soc/intel/cannonlake/acpi/xhci.asl
@@ -1,13 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <intelblocks/xhci.h>
#include <soc/gpe.h>
-#define PORTSCN_OFFSET 0x480
-#define PORTSCXUSB3_OFFSET 0x540
-
-#define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000
-#define RO_BITS_OFF_MASK ~0x80FE0012
-
/*
* USB Port Wake Enable (UPWE) on usb attach/detach
* Arg0 - Port Number
@@ -25,14 +20,8 @@ Method (UPWE, 3, Serialized)
PSCT, 32,
}
Local0 = PSCT
- /*
- * And port status/control reg with RO and RWS bits
- * RO bits: 0, 2:3, 10:13, 24, 28:30
- * RWS bits: 5:9, 14:16, 25:27
- */
- Local0 = Local0 & RO_BITS_OFF_MASK
- /* Set WCE and WDE bits */
- Local0 = Local0 | WAKE_ON_CONNECT_DISCONNECT_ENABLE
+ Local0 = Local0 & PORTSCN_BITS_OFF_MASK
+ Local0 = Local0 | PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE
PSCT = Local0
}
diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h
index 8c58891d61..15b16d2073 100644
--- a/src/soc/intel/common/block/include/intelblocks/xhci.h
+++ b/src/soc/intel/common/block/include/intelblocks/xhci.h
@@ -3,6 +3,20 @@
#ifndef SOC_INTEL_COMMON_BLOCK_XHCI_H
#define SOC_INTEL_COMMON_BLOCK_XHCI_H
+#define PORTSCN_OFFSET 0x480
+#define PORTSCN_WAKE_ON_DISCONNECT_ENABLE 0x4000000
+#define PORTSCN_WAKE_ON_CONNECT_ENABLE 0x2000000
+/* Set WDE and WCE bits */
+#define PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE 0x6000000
+/*
+ * And port status/control reg with RO and RWS bits
+ * RO bits: 0, 2:3, 10:13, 24, 28:30
+ * RWS bits: 5:9, 14:16, 25:27
+ */
+#define PORTSCN_BITS_OFF_MASK ~0x80FE0012
+#define PORTSCXUSB3_OFFSET 0x540
+
+#if !defined(__ACPI__)
#include <device/device.h>
#include <device/xhci.h>
#include <elog.h>
@@ -63,5 +77,5 @@ const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev);
*/
void usb_xhci_disable_unused(bool (*ext_usb_xhci_en_cb)(unsigned int port_type,
unsigned int port_id));
-
+#endif /* if !defined(__ACPI__) */
#endif /* SOC_INTEL_COMMON_BLOCK_XHCI_H */
diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl
index e8c5ebf27e..0540919e37 100644
--- a/src/soc/intel/skylake/acpi/xhci.asl
+++ b/src/soc/intel/skylake/acpi/xhci.asl
@@ -1,10 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#define PORTSCN_OFFSET 0x480
-#define PORTSCXUSB3_OFFSET 0x540
-
-#define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000
-#define RO_BITS_OFF_MASK ~0x80FE0012
+#include <intelblocks/xhci.h>
/*
* USB Port Wake Enable (UPWE) on usb attach/detach
@@ -23,14 +19,8 @@ Method (UPWE, 3, Serialized)
PSCT, 32,
}
Local0 = PSCT
- /*
- * And port status/control reg with RO and RWS bits
- * RO bits: 0, 2:3, 10:13, 24, 28:30
- * RWS bits: 5:9, 14:16, 25:27
- */
- Local0 = Local0 & RO_BITS_OFF_MASK
- /* Set WCE and WDE bits */
- Local0 = Local0 | WAKE_ON_CONNECT_DISCONNECT_ENABLE
+ Local0 = Local0 & PORTSCN_BITS_OFF_MASK
+ Local0 = Local0 | PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE
PSCT = Local0
}