4 files changed, 0 insertions, 42 deletions
diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc
index 390fd9783e..f30360f766 100644
--- a/src/southbridge/intel/i82371eb/Makefile.inc
+++ b/src/southbridge/intel/i82371eb/Makefile.inc
@@ -23,7 +23,6 @@ ramstage-y +=  isa.c
 ramstage-y +=  ide.c
 ramstage-y +=  usb.c
 ramstage-y +=  smbus.c
-ramstage-y +=  reset.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c
 ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c
diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c
index 4d98a3083d..898cdffc25 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.c
+++ b/src/southbridge/intel/i82371eb/i82371eb.c
@@ -47,14 +47,7 @@
 /* TODO: List the other datasheets. */
 
 #include <device/device.h>
-#include "i82371eb.h"
-
-void i82371eb_enable(struct device *dev)
-{
-	/* TODO: Nothing to do? */
-}
 
 const struct chip_operations southbridge_intel_i82371eb_ops = {
 	CHIP_NAME("Intel 82371FB/SB/MX/AB/EB/MB Southbridge")
-	.enable_dev = i82371eb_enable,
 };
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index d35b215ab1..55242effca 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -19,11 +19,6 @@
 
 #if !defined(__ACPI__)
 
-#include <device/device.h>
-void i82371eb_enable(struct device *dev);
-
-void i82371eb_hard_reset(void);
-
 void enable_smbus(void);
 void enable_pm(void);
 
@@ -45,7 +40,6 @@ int smbus_read_byte(u8 device, u8 address);
 
 #define XBCS		0x4e	/* X-Bus chip select register */
 #define GENCFG		0xb0	/* General configuration register */
-#define RC		0xcf9	/* Reset control register */
 
 /* IDE */
 #define IDETIM_PRI	0x40	/* IDE timing register, primary channel */
@@ -115,8 +109,6 @@ int smbus_read_byte(u8 device, u8 address);
 #define EXT_BIOS_ENABLE		(1 << 7)  /* Extended BIOS Enable */
 #define LOWER_BIOS_ENABLE	(1 << 6)  /* Lower BIOS Enable */
 #define WRITE_PROTECT_ENABLE	(1 << 2)  /* Write Protect Enable */
-#define SRST			(1 << 1)  /* System Reset */
-#define RCPU			(1 << 2)  /* Reset CPU */
 #define SMB_HST_EN		(1 << 0)  /* Host Interface Enable */
 #define IDE_DECODE_ENABLE	(1 << 15) /* IDE Decode Enable */
 #define DTE0			(1 << 3)  /* DMA Timing Enable Only, drive 0 */
diff --git a/src/southbridge/intel/i82371eb/reset.c b/src/southbridge/intel/i82371eb/reset.c
deleted file mode 100644
index 1d1dd640b9..0000000000
--- a/src/southbridge/intel/i82371eb/reset.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include "i82371eb.h"
-
-/**
- * Initiate a hard reset.
- */
-void i82371eb_hard_reset(void)
-{
-	outb(SRST | RCPU, RC);
-}