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-rw-r--r--src/soc/amd/sabrina/fch.c1
-rw-r--r--src/soc/amd/sabrina/include/soc/southbridge.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/sabrina/fch.c b/src/soc/amd/sabrina/fch.c
index 533eb9489c..7368222338 100644
--- a/src/soc/amd/sabrina/fch.c
+++ b/src/soc/amd/sabrina/fch.c
@@ -178,6 +178,7 @@ static void cgpll_clock_gate_init(void)
t = misc_read32(MISC_CLKGATEDCNTL);
t |= ALINKCLK_GATEOFFEN;
t |= BLINKCLK_GATEOFFEN;
+ t |= XTAL_PAD_S0I3_TURNOFF_EN;
t |= XTAL_PAD_S3_TURNOFF_EN;
t |= XTAL_PAD_S5_TURNOFF_EN;
misc_write32(MISC_CLKGATEDCNTL, t);
diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h
index d72696285d..789e73ff83 100644
--- a/src/soc/amd/sabrina/include/soc/southbridge.h
+++ b/src/soc/amd/sabrina/include/soc/southbridge.h
@@ -105,6 +105,7 @@
#define MISC_CLKGATEDCNTL 0x2c
#define ALINKCLK_GATEOFFEN BIT(16)
#define BLINKCLK_GATEOFFEN BIT(17)
+#define XTAL_PAD_S0I3_TURNOFF_EN BIT(19)
#define XTAL_PAD_S3_TURNOFF_EN BIT(20)
#define XTAL_PAD_S5_TURNOFF_EN BIT(21)
#define MISC_CGPLL_CONFIGURATION0 0x30