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-rw-r--r--src/drivers/intel/fsp2_0/debug.c12
-rw-r--r--src/drivers/intel/fsp2_0/include/fsp/debug.h6
-rw-r--r--src/drivers/intel/fsp2_0/include/fsp/util.h15
-rw-r--r--src/drivers/intel/fsp2_0/memory_init.c12
-rw-r--r--src/drivers/intel/fsp2_0/silicon_init.c16
-rw-r--r--src/drivers/intel/fsp2_0/util.c6
-rw-r--r--src/include/efi/efi_datatype.h6
-rw-r--r--src/soc/amd/common/fsp/fsp_reset.c5
-rw-r--r--src/soc/intel/common/fsp_reset.c6
9 files changed, 48 insertions, 36 deletions
diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c
index 4cd309e7e7..9dc964d303 100644
--- a/src/drivers/intel/fsp2_0/debug.c
+++ b/src/drivers/intel/fsp2_0/debug.c
@@ -85,10 +85,10 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
printk(BIOS_SPEW, "\t%p: &hob_list_ptr\n", fsp_get_hob_list_ptr());
}
-void fsp_debug_after_memory_init(uint32_t status)
+void fsp_debug_after_memory_init(efi_return_status_t status)
{
if (CONFIG(DISPLAY_FSP_CALLS_AND_STATUS))
- printk(BIOS_SPEW, "FspMemoryInit returned 0x%08x\n", status);
+ fsp_printk(status, BIOS_SPEW, "FspMemoryInit");
if (status != FSP_SUCCESS)
return;
@@ -130,13 +130,13 @@ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init,
printk(BIOS_SPEW, "\t%p: upd\n", fsps_new_upd);
}
-void fsp_debug_after_silicon_init(uint32_t status)
+void fsp_debug_after_silicon_init(efi_return_status_t status)
{
if (CONFIG(CHECK_GPIO_CONFIG_CHANGES))
fsp_gpio_config_check(AFTER_FSP_CALL, "FSP Silicon Init");
if (CONFIG(DISPLAY_FSP_CALLS_AND_STATUS))
- printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status);
+ fsp_printk(status, BIOS_SPEW, "FspSiliconInit");
/* Display the HOBs */
if (CONFIG(DISPLAY_HOBS))
@@ -164,13 +164,13 @@ void fsp_before_debug_notify(fsp_notify_fn notify,
printk(BIOS_SPEW, "\t%p: notify_params\n", notify_params);
}
-void fsp_debug_after_notify(uint32_t status)
+void fsp_debug_after_notify(efi_return_status_t status)
{
if (CONFIG(CHECK_GPIO_CONFIG_CHANGES))
fsp_gpio_config_check(AFTER_FSP_CALL, "FSP Notify");
if (CONFIG(DISPLAY_FSP_CALLS_AND_STATUS))
- printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", status);
+ fsp_printk(status, BIOS_SPEW, "FspNotify");
/* Display the HOBs */
if (CONFIG(DISPLAY_HOBS))
diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h
index dc5557e231..e7f9f25486 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/debug.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h
@@ -19,14 +19,14 @@ enum fsp_log_level fsp_map_console_log_level(void);
void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
const FSPM_UPD *fspm_old_upd,
const FSPM_UPD *fspm_new_upd);
-void fsp_debug_after_memory_init(uint32_t status);
+void fsp_debug_after_memory_init(efi_return_status_t status);
void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init,
const FSPS_UPD *fsps_old_upd,
const FSPS_UPD *fsps_new_upd);
-void fsp_debug_after_silicon_init(uint32_t status);
+void fsp_debug_after_silicon_init(efi_return_status_t status);
void fsp_before_debug_notify(fsp_notify_fn notify,
const struct fsp_notify_params *notify_params);
-void fsp_debug_after_notify(uint32_t status);
+void fsp_debug_after_notify(efi_return_status_t status);
void fspm_display_upd_values(const FSPM_UPD *old,
const FSPM_UPD *new);
void fsp_display_hobs(void);
diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h
index bed4fcb29e..e89b7f8205 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/util.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/util.h
@@ -31,6 +31,17 @@ do { \
memcpy(dst, src, sizeof(src)); \
} while (0)
+/* Helper function to print a message concatenated with the a FSP return status. */
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
+#define FSP_STATUS_FMT "0x%08x"
+#else
+#define FSP_STATUS_FMT "0x%016llx"
+#endif
+#define fsp_printk(status, msg_level, fmt, ...) \
+ printk(msg_level, fmt ", status=" FSP_STATUS_FMT "\n", ##__VA_ARGS__, status)
+#define fsp_die_with_post_code(status, postcode, fmt, ...) \
+ die_with_post_code(postcode, fmt ", status=" FSP_STATUS_FMT "\n", ##__VA_ARGS__, status)
+
struct hob_header {
uint16_t type;
uint16_t length;
@@ -187,10 +198,10 @@ enum cb_err fsp_load_component(struct fsp_load_descriptor *fspld, struct fsp_hea
* SoC. If the requested status is not a reboot status or unhandled, this
* function does nothing.
*/
-void fsp_handle_reset(uint32_t status);
+void fsp_handle_reset(efi_return_status_t status);
/* SoC/chipset must provide this to handle platform-specific reset codes */
-void chipset_handle_reset(uint32_t status);
+void chipset_handle_reset(efi_return_status_t status);
#if CONFIG(PLATFORM_USES_SECOND_FSP)
/* The SoC must implement these to choose the appropriate FSP-M/FSP-S binary. */
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index dc725c3561..31ae21336c 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -274,22 +274,22 @@ static uint32_t fsp_mrc_version(const struct fsp_header *hdr)
return ver;
}
-static void fspm_return_value_handler(const char *context, uint32_t status, bool die_on_error)
+static void fspm_return_value_handler(const char *context, efi_return_status_t status,
+ bool die_on_error)
{
if (status == FSP_SUCCESS)
return;
fsp_handle_reset(status);
if (die_on_error)
- die_with_post_code(POSTCODE_RAM_FAILURE, "%s returned with error 0x%zx!\n",
- context, (size_t)status);
+ fsp_die_with_post_code(status, POSTCODE_RAM_FAILURE, "%s error", context);
- printk(BIOS_SPEW, "%s returned 0x%zx\n", context, (size_t)status);
+ fsp_printk(status, BIOS_SPEW, "%s", context);
}
static void fspm_multi_phase_init(const struct fsp_header *hdr)
{
- uint32_t status;
+ efi_return_status_t status;
fsp_multi_phase_init_fn fsp_multi_phase_init;
struct fsp_multi_phase_params multi_phase_params;
struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number;
@@ -332,7 +332,7 @@ static void fspm_multi_phase_init(const struct fsp_header *hdr)
static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
{
- uint32_t status;
+ efi_return_status_t status;
fsp_memory_init_fn fsp_raminit;
FSPM_UPD fspm_upd, *upd;
FSPM_ARCHx_UPD *arch_upd;
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 08258d3f26..52d714d503 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -36,7 +36,8 @@ enum fsp_silicon_init_phases {
FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API
};
-static void fsps_return_value_handler(enum fsp_silicon_init_phases phases, uint32_t status)
+static void fsps_return_value_handler(enum fsp_silicon_init_phases phases,
+ efi_return_status_t status)
{
uint8_t postcode;
@@ -54,16 +55,13 @@ static void fsps_return_value_handler(enum fsp_silicon_init_phases phases, uint3
switch (phases) {
case FSP_SILICON_INIT_API:
- die_with_post_code(postcode, "FspSiliconInit returned with error 0x%08x\n",
- status);
+ fsp_die_with_post_code(status, postcode, "FspSiliconInit error");
break;
case FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API:
- printk(BIOS_SPEW, "FspMultiPhaseSiInit NumberOfPhases returned 0x%08x\n",
- status);
+ fsp_printk(status, BIOS_SPEW, "FspMultiPhaseSiInit NumberOfPhases");
break;
case FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API:
- printk(BIOS_SPEW, "FspMultiPhaseSiInit ExecutePhase returned 0x%08x\n",
- status);
+ fsp_printk(status, BIOS_SPEW, "FspMultiPhaseSiInit ExecutePhase");
break;
default:
break;
@@ -88,7 +86,7 @@ static void do_silicon_init(struct fsp_header *hdr)
{
FSPS_UPD *upd, *supd;
fsp_silicon_init_fn silicon_init;
- uint32_t status;
+ efi_return_status_t status;
fsp_multi_phase_init_fn multi_phase_si_init;
struct fsp_multi_phase_params multi_phase_params;
struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number;
@@ -139,7 +137,7 @@ static void do_silicon_init(struct fsp_header *hdr)
status = silicon_init(upd);
null_breakpoint_init();
- printk(BIOS_INFO, "FSPS returned %x\n", status);
+ fsp_printk(status, BIOS_INFO, "FSPS");
timestamp_add_now(TS_FSP_SILICON_INIT_END);
post_code(POSTCODE_FSP_SILICON_EXIT);
diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
index f912d9acab..47dc3e8229 100644
--- a/src/drivers/intel/fsp2_0/util.c
+++ b/src/drivers/intel/fsp2_0/util.c
@@ -83,18 +83,18 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, void *fsp_file, size_
return CB_SUCCESS;
}
-static bool fsp_reset_requested(uint32_t status)
+static bool fsp_reset_requested(efi_return_status_t status)
{
return (status >= FSP_STATUS_RESET_REQUIRED_COLD &&
status <= FSP_STATUS_RESET_REQUIRED_8);
}
-void fsp_handle_reset(uint32_t status)
+void fsp_handle_reset(efi_return_status_t status)
{
if (!fsp_reset_requested(status))
return;
- printk(BIOS_SPEW, "FSP: handling reset type %x\n", status);
+ fsp_printk(status, BIOS_SPEW, "FSP: handling reset type");
switch (status) {
case FSP_STATUS_RESET_REQUIRED_COLD:
diff --git a/src/include/efi/efi_datatype.h b/src/include/efi/efi_datatype.h
index 31612b84c9..8a1a124d5a 100644
--- a/src/include/efi/efi_datatype.h
+++ b/src/include/efi/efi_datatype.h
@@ -65,7 +65,11 @@ typedef UINTN efi_uintn_t;
/* Signed value of native width. */
typedef INTN efi_intn_t;
/* Status codes common to all execution phases */
-typedef EFI_STATUS efi_return_status_t;
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
+typedef UINT32 efi_return_status_t;
+#else
+typedef UINT64 efi_return_status_t;
+#endif
/* Data structure for EFI_PHYSICAL_ADDRESS */
typedef EFI_PHYSICAL_ADDRESS efi_physical_address;
/* 128-bit buffer containing a unique identifier value */
diff --git a/src/soc/amd/common/fsp/fsp_reset.c b/src/soc/amd/common/fsp/fsp_reset.c
index 0a89dc728a..761ba2bdbb 100644
--- a/src/soc/amd/common/fsp/fsp_reset.c
+++ b/src/soc/amd/common/fsp/fsp_reset.c
@@ -6,10 +6,9 @@
#include <fsp/util.h>
#include <stdint.h>
-void chipset_handle_reset(uint32_t status)
+void chipset_handle_reset(efi_return_status_t status)
{
- printk(BIOS_ERR, "unexpected call to %s(0x%08x). Doing cold reset.\n",
- __func__, status);
+ fsp_printk(status, BIOS_ERR, "Doing cold reset due to unexpected call to %s", __func__);
BUG();
do_cold_reset();
}
diff --git a/src/soc/intel/common/fsp_reset.c b/src/soc/intel/common/fsp_reset.c
index 2bb39bd5a3..2626c39413 100644
--- a/src/soc/intel/common/fsp_reset.c
+++ b/src/soc/intel/common/fsp_reset.c
@@ -30,20 +30,20 @@ struct fsp_reset_hob {
struct pch_reset_data reset_data;
};
-void chipset_handle_reset(uint32_t status)
+void chipset_handle_reset(efi_return_status_t status)
{
if (status == CONFIG_FSP_STATUS_GLOBAL_RESET) {
printk(BIOS_DEBUG, "GLOBAL RESET!\n");
global_reset();
}
- printk(BIOS_ERR, "unhandled reset type %x\n", status);
+ fsp_printk(status, BIOS_ERR, "unhandled reset type");
die("unknown reset type");
}
static uint32_t fsp_reset_type_to_status(EFI_RESET_TYPE reset_type)
{
- uint32_t status;
+ efi_return_status_t status;
switch (reset_type) {
case EfiResetCold:
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 23:32:23 +0000