summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb1
-rw-r--r--src/mainboard/starlabs/starbook/variants/tgl/devtree.c1
-rw-r--r--src/soc/intel/tigerlake/chip.h2
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c2
4 files changed, 1 insertions, 5 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index cd8c48071a..c3a3f45546 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -19,7 +19,6 @@ chip soc/intel/tigerlake
register "CnviBtAudioOffload" = "1"
register "enable_c6dram" = "1"
register "SaGv" = "SaGv_Enabled"
- register "TcssD3ColdDisable" = "1"
# FSP Silicon
# Serial I/O
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
index 1c280c4a34..0077a63604 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c
@@ -60,7 +60,6 @@ void devtree_update(void)
if (get_uint_option("thunderbolt", 1) == 0) {
cfg->UsbTcPortEn = 0;
cfg->TcssXhciEn = 0;
- cfg->TcssD3ColdDisable = 0;
tbt_pci_dev->enabled = 0;
tbt_dma_dev->enabled = 0;
}
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 6aa040840e..3de8ffaf43 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -148,8 +148,6 @@ struct soc_intel_tigerlake_config {
/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
uint8_t TcssD3HotDisable;
- /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
- uint8_t TcssD3ColdDisable;
/* Enable DPTF support */
int dptf_enable;
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index b823f50301..358536ea43 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -327,7 +327,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
if (cpu_id == CPUID_TIGERLAKE_A0)
params->D3ColdEnable = 0;
else
- params->D3ColdEnable = !config->TcssD3ColdDisable;
+ params->D3ColdEnable = CONFIG(D3COLD_SUPPORT);
params->UsbTcPortEn = config->UsbTcPortEn;
params->TcssAuxOri = config->TcssAuxOri;