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-rw-r--r--src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb2
-rw-r--r--src/mainboard/google/brya/variants/marasov/overridetree.cb2
-rw-r--r--src/mainboard/intel/adlrvp/devicetree_n.cb2
-rw-r--r--src/soc/intel/alderlake/Kconfig14
-rw-r--r--src/soc/intel/alderlake/chip.h6
-rw-r--r--src/soc/intel/alderlake/romstage/fsp_params.c2
6 files changed, 15 insertions, 13 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index 16c7ce02df..ad5b1f8dbc 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -89,8 +89,6 @@ chip soc/intel/alderlake
# Disable Package C-state demotion for nissa baseboard.
register "disable_package_c_state_demotion" = "1"
- register "skip_mbp_hob" = "1"
-
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb
index e09166df69..4cc87907d6 100644
--- a/src/mainboard/google/brya/variants/marasov/overridetree.cb
+++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb
@@ -66,8 +66,6 @@ chip soc/intel/alderlake
}"
register "sagv" = "SaGv_Enabled"
- register "skip_mbp_hob" = "1"
-
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb
index b54a134530..6776284fe0 100644
--- a/src/mainboard/intel/adlrvp/devicetree_n.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_n.cb
@@ -150,8 +150,6 @@ chip soc/intel/alderlake
.vnn_icc_max_ma = 500,
}"
- register "skip_mbp_hob" = "1"
-
device domain 0 on
device ref igpu on end
device ref dtt on
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 9c5868b0d6..afa2a752df 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -537,4 +537,18 @@ config INTEL_GMA_BCLM_OFFSET
config INTEL_GMA_BCLM_WIDTH
default 32
+config FSP_PUBLISH_MBP_HOB
+ bool
+ default n if CHROMEOS && (SOC_INTEL_RAPTORLAKE || SOC_INTEL_ALDERLAKE_PCH_N)
+ default y
+ help
+ This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
+ Disabling it for the platforms, which do not use MBP HOB, can improve the boot time.
+
+ Note: It cannot be disabled for ADL-P based platforms because ADL-P FSP relies on
+ MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't
+ occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the
+ later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based
+ platforms.
+
endif
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 33549bcc72..cea63bf466 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -667,12 +667,6 @@ struct soc_intel_alderlake_config {
*/
bool disable_package_c_state_demotion;
- /*
- * Enable or Disable Skipping MBP HOB.
- * Default is set to 0 and set to 1 to skip the MBP HOB.
- */
- bool skip_mbp_hob;
-
/* i915 struct for GMA backlight control */
struct i915_gpu_controller_info gfx;
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index df94e487a4..6016bffa1a 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -230,7 +230,7 @@ static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg,
m_cfg->CnviDdrRfim = wifi_generic_cnvi_ddr_rfim_enabled(dev);
/* Skip MBP HOB */
- m_cfg->SkipMbpHob = config->skip_mbp_hob;
+ m_cfg->SkipMbpHob = !CONFIG(FSP_PUBLISH_MBP_HOB);
}
static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,