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-rw-r--r--src/cpu/amd/agesa/s3_resume.c42
-rw-r--r--src/cpu/amd/agesa/s3_resume.h5
-rw-r--r--src/mainboard/amd/olivehill/romstage.c25
-rw-r--r--src/mainboard/amd/parmer/romstage.c25
-rw-r--r--src/mainboard/amd/persimmon/romstage.c26
-rw-r--r--src/mainboard/amd/thatcher/romstage.c25
-rw-r--r--src/mainboard/asrock/imb-a180/romstage.c25
-rw-r--r--src/mainboard/asus/f2a85-m/romstage.c25
-rwxr-xr-xsrc/mainboard/gizmosphere/gizmo/romstage.c26
-rw-r--r--src/mainboard/hp/pavilion_m6_1035dx/romstage.c25
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/romstage.c26
-rw-r--r--src/mainboard/lippert/frontrunner-af/romstage.c26
-rw-r--r--src/mainboard/lippert/toucan-af/romstage.c26
13 files changed, 42 insertions, 285 deletions
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 2efe6be0cb..42447862eb 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -22,6 +22,7 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/amd/car.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/cache.h>
#include <cbmem.h>
@@ -142,7 +143,8 @@ void restore_mtrr(void)
wrmsr(SYS_CFG, msr_data);
}
-void *backup_resume(void)
+#ifdef __PRE_RAM__
+static void *backup_resume(void)
{
void *resume_backup_memory;
@@ -160,7 +162,7 @@ void *backup_resume(void)
return resume_backup_memory;
}
-void move_stack_high_mem(void)
+static void move_stack_high_mem(void)
{
void *high_stack;
@@ -173,6 +175,7 @@ void move_stack_high_mem(void)
(high_stack - BSP_STACK_BASE_ADDR)
:);
}
+#endif
#ifndef __PRE_RAM__
static void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx)
@@ -306,7 +309,8 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
}
#endif
-void set_resume_cache(void)
+#ifdef __PRE_RAM__
+static void set_resume_cache(void)
{
msr_t msr;
@@ -331,14 +335,28 @@ void set_resume_cache(void)
enable_cache();
}
-void s3_resume(void)
+void prepare_for_resume(void)
{
- int status;
-
- printk(BIOS_DEBUG, "agesawrapper_amds3laterestore ");
- status = agesawrapper_amds3laterestore();
- if (status)
- printk(BIOS_DEBUG, "error level: %x \n", (u32) status);
- else
- printk(BIOS_DEBUG, "passed.\n");
+ printk(BIOS_DEBUG, "Find resume memory location\n");
+ void *resume_backup_memory = backup_resume();
+
+ post_code(0x62);
+ printk(BIOS_DEBUG, "Move CAR stack.\n");
+ move_stack_high_mem();
+ printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
+
+ post_code(0x63);
+ disable_cache_as_ram();
+ printk(BIOS_DEBUG, "CAR disabled.\n");
+ set_resume_cache();
+
+ /*
+ * Copy the system memory that is in the ramstage area to the
+ * reserved area.
+ */
+ if (resume_backup_memory)
+ memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
+
+ printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
}
+#endif
diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h
index fd3f29ea4c..b72e8a2600 100644
--- a/src/cpu/amd/agesa/s3_resume.h
+++ b/src/cpu/amd/agesa/s3_resume.h
@@ -27,10 +27,7 @@ typedef enum {
} S3_DATA_TYPE;
void restore_mtrr(void);
-void s3_resume(void);
-void *backup_resume(void);
-void set_resume_cache(void);
-void move_stack_high_mem(void);
+void prepare_for_resume(void);
u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data);
void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data);
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 8d2156e507..dc52d16688 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -41,9 +41,6 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
@@ -133,27 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = (void *)backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 36a6b8a175..8c0afa5801 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -41,9 +41,6 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
val = agesawrapper_amdinitmmio();
hudson_lpc_port80();
@@ -116,27 +113,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = (void *)backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 5908421545..32b85c3b8e 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -50,10 +50,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
-
/*
* All cores: allow caching of flash chip code and data
* (there are no cache-as-ram reliability concerns with family 14h)
@@ -145,27 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 1461c4c786..063d2d9d86 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
u8 byte;
device_t dev;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
val = agesawrapper_amdinitmmio();
hudson_lpc_port80();
@@ -133,27 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = (void *)backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 382ad5bb99..8ed5e05626 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val, t32;
u32 *addr32;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
@@ -157,27 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = (void *)backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 03f4bb1767..c8e102bfc7 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -75,9 +75,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80();
#endif
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
val = agesawrapper_amdinitmmio();
if (!cpu_init_detectedx && boot_cpu()) {
@@ -181,27 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = (void *)backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 63a2be861e..c6119926a6 100755
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -51,10 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
msr_t msr;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
-
/*
* All cores: allow caching of flash chip code and data
* (there are no cache-as-ram reliability concerns with family 14h)
@@ -153,27 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
index cb4268cc35..4b433c9f0b 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
@@ -38,9 +38,6 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
val = agesawrapper_amdinitmmio();
hudson_lpc_port80();
@@ -113,27 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = (void *)backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 25459d7d90..b49ea81a0c 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -66,10 +66,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
-
/*
* All cores: allow caching of flash chip code and data
* (there are no cache-as-ram reliability concerns with family 14h)
@@ -161,27 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif /* CONFIG_HAVE_ACPI_RESUME */
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index 794588311e..06b365a0d2 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -49,10 +49,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
-
/*
* All cores: allow caching of flash chip code and data
* (there are no cache-as-ram reliability concerns with family 14h)
@@ -148,27 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index b8bd744522..6a5c580dcb 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -50,10 +50,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
-
/*
* All cores: allow caching of flash chip code and data
* (there are no cache-as-ram reliability concerns with family 14h)
@@ -149,27 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
- printk(BIOS_DEBUG, "Find resume memory location\n");
- resume_backup_memory = backup_resume();
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
- /*
- * Copy the system memory that is in the ramstage area to the
- * reserved area.
- */
- if (resume_backup_memory)
- memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
-
- printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ prepare_for_resume();
}
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 06:16:55 +0000