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-rw-r--r--src/soc/amd/picasso/chip.h15
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h58
-rw-r--r--src/soc/amd/picasso/southbridge.c74
3 files changed, 2 insertions, 145 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 2b9ef3c37a..8d4e0d3875 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -73,21 +73,6 @@ struct soc_amd_picasso_config {
uint8_t min_soc_vid_offset;
uint8_t aclk_dpm0_freq_400MHz;
- /*
- * SPI config
- * Default values if not overridden by mainboard:
- * Read mode - Normal 33MHz
- * Normal speed - 66MHz
- * Fast speed - 66MHz
- * Alt speed - 66MHz
- * TPM speed - 66MHz
- */
- enum spi_read_mode spi_read_mode;
- enum spi100_speed spi_normal_speed;
- enum spi100_speed spi_fast_speed;
- enum spi100_speed spi_altio_speed;
- enum spi100_speed spi_tpm_speed;
-
enum {
SD_EMMC_DISABLE,
SD_EMMC_SD_LOW_SPEED,
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 602647660a..5bae754cf6 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -240,61 +240,6 @@
#define SATA_CAPABILITIES_REG 0xfc
#define SATA_CAPABILITY_SPM BIT(12)
-#define SPI_CNTRL0 0x00
-#define SPI_BUSY BIT(31)
-enum spi_read_mode {
- SPI_READ_MODE_NORMAL33M = 0,
- /* 1 is reserved. */
- SPI_READ_MODE_DUAL112 = 2,
- SPI_READ_MODE_QUAD114 = 3,
- SPI_READ_MODE_DUAL122 = 4,
- SPI_READ_MODE_QUAD144 = 5,
- SPI_READ_MODE_NORMAL66M = 6,
- SPI_READ_MODE_FAST_READ = 7,
-};
-/*
- * SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for
- * SpiReadMode.
- */
-#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))
-#define SPI_READ_MODE_UPPER_BITS(x) ((((x) >> 1) & 0x3) << 29)
-#define SPI_READ_MODE_LOWER_BITS(x) (((x) & 0x1) << 18)
-#define SPI_READ_MODE(x) (SPI_READ_MODE_UPPER_BITS(x) | \
- SPI_READ_MODE_LOWER_BITS(x))
-#define SPI_ACCESS_MAC_ROM_EN BIT(22)
-#define SPI_FIFO_PTR_CLR BIT(20)
-#define SPI_ARB_ENABLE BIT(19)
-#define EXEC_OPCODE BIT(16)
-#define SPI_FIFO 0x80
-#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO)
-
-#define SPI100_ENABLE 0x20
-#define SPI_USE_SPI100 BIT(0)
-
-/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */
-#define SPI100_SPEED_CONFIG 0x22
-enum spi100_speed {
- SPI_SPEED_66M = 0,
- SPI_SPEED_33M = 1,
- SPI_SPEED_22M = 2,
- SPI_SPEED_16M = 3,
- SPI_SPEED_100M = 4,
- SPI_SPEED_800K = 5,
-};
-
-#define SPI_SPEED_MASK 0xf
-#define SPI_SPEED_MODE(x, shift) (((x) & SPI_SPEED_MASK) << (shift))
-#define SPI_NORM_SPEED(x) SPI_SPEED_MODE(x, 12)
-#define SPI_FAST_SPEED(x) SPI_SPEED_MODE(x, 8)
-#define SPI_ALT_SPEED(x) SPI_SPEED_MODE(x, 4)
-#define SPI_TPM_SPEED(x) SPI_SPEED_MODE(x, 0)
-
-#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \
- SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t))
-
-#define SPI100_HOST_PREF_CONFIG 0x2c
-#define SPI_RD4DW_EN_HOST BIT(15)
-
/* IO 0xcf9 - Reset control port*/
#define FULL_RST BIT(3)
#define RST_CMD BIT(2)
@@ -329,12 +274,9 @@ struct soc_power_reg {
void enable_aoac_devices(void);
void sb_clk_output_48Mhz(void);
-void sb_disable_4dw_burst(void);
void sb_enable(struct device *dev);
void southbridge_final(void *chip_info);
void southbridge_init(void *chip_info);
-void sb_read_mode(u32 mode);
-void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
void fch_pre_init(void);
void fch_early_init(void);
void set_uart_config(int idx);
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 6308953fc6..c871ec9f58 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -14,6 +14,7 @@
#include <amdblocks/acpimmio.h>
#include <amdblocks/lpc.h>
#include <amdblocks/acpi.h>
+#include <amdblocks/spi.h>
#include <soc/cpu.h>
#include <soc/southbridge.h>
#include <soc/smi.h>
@@ -197,77 +198,6 @@ void sb_clk_output_48Mhz(void)
misc_write32(MISC_CLK_CNTL1, ctrl);
}
-static uintptr_t sb_init_spi_base(void)
-{
- uintptr_t base;
-
- /* Make sure the base address is predictable */
- base = lpc_get_spibase();
-
- if (base)
- return base;
-
- lpc_set_spibase(SPI_BASE_ADDRESS);
- lpc_enable_spi_rom(SPI_ROM_ENABLE);
-
- return SPI_BASE_ADDRESS;
-}
-
-void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
-{
- uintptr_t base = sb_init_spi_base();
-
- write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm));
- write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100);
-}
-
-void sb_disable_4dw_burst(void)
-{
- uintptr_t base = sb_init_spi_base();
- write16((void *)(base + SPI100_HOST_PREF_CONFIG),
- read16((void *)(base + SPI100_HOST_PREF_CONFIG))
- & ~SPI_RD4DW_EN_HOST);
-}
-
-void sb_read_mode(u32 mode)
-{
- uintptr_t base = sb_init_spi_base();
- uint32_t val = (read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK);
-
- write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode));
-}
-
-static void sb_spi_config_mb_modes(void)
-{
- const struct soc_amd_picasso_config *cfg = config_of_soc();
-
- sb_read_mode(cfg->spi_read_mode);
- sb_set_spi100(cfg->spi_normal_speed, cfg->spi_fast_speed, cfg->spi_altio_speed,
- cfg->spi_tpm_speed);
-}
-
-static void sb_spi_config_em100_modes(void)
-{
- sb_read_mode(SPI_READ_MODE_NORMAL33M);
- sb_set_spi100(SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M);
-}
-
-static void sb_spi_config_modes(void)
-{
- if (CONFIG(EM100))
- sb_spi_config_em100_modes();
- else
- sb_spi_config_mb_modes();
-}
-
-static void sb_spi_init(void)
-{
- lpc_enable_spi_prefetch();
- sb_init_spi_base();
- sb_disable_4dw_burst();
- sb_spi_config_modes();
-}
-
static void fch_smbus_init(void)
{
/* 400 kHz smbus speed. */
@@ -293,7 +223,7 @@ void fch_pre_init(void)
if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)
&& CONFIG(PICASSO_LPC_IOMUX))
lpc_enable_port80();
- sb_spi_init();
+ fch_spi_early_init();
enable_acpimmio_decode_pm04();
fch_smbus_init();
sb_enable_cf9_io();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 07:34:38 +0000