diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/device/dram/spd.c | 16 | ||||
| -rw-r--r-- | src/include/device/dram/ddr5.h | 28 |
2 files changed, 22 insertions, 22 deletions
diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c index e33a26ad68..41ec7c52c7 100644 --- a/src/device/dram/spd.c +++ b/src/device/dram/spd.c @@ -135,26 +135,26 @@ static void convert_ddr4_module_type_to_spd_info(enum spd_dimm_type_ddr4 module_ } } -static void convert_ddr5_module_type_to_spd_info(enum ddr5_module_type module_type, +static void convert_ddr5_module_type_to_spd_info(enum spd_dimm_type_ddr5 module_type, struct spd_info *info) { switch (module_type) { - case DDR5_SPD_RDIMM: - case DDR5_SPD_MINI_RDIMM: + case SPD_DDR5_DIMM_TYPE_RDIMM: + case SPD_DDR5_DIMM_TYPE_MINI_RDIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; break; - case DDR5_SPD_UDIMM: - case DDR5_SPD_MINI_UDIMM: + case SPD_DDR5_DIMM_TYPE_UDIMM: + case SPD_DDR5_DIMM_TYPE_MINI_UDIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; break; - case DDR5_SPD_SODIMM: - case DDR5_SPD_72B_SO_UDIMM: + case SPD_DDR5_DIMM_TYPE_SODIMM: + case SPD_DDR5_DIMM_TYPE_72B_SO_UDIMM: info->form_factor = MEMORY_FORMFACTOR_SODIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; break; - case DDR5_SPD_2DPC: + case SPD_DDR5_DIMM_TYPE_2DPC: info->form_factor = MEMORY_FORMFACTOR_PROPRIETARY_CARD; info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; break; diff --git a/src/include/device/dram/ddr5.h b/src/include/device/dram/ddr5.h index 37182da365..78d18b24f8 100644 --- a/src/include/device/dram/ddr5.h +++ b/src/include/device/dram/ddr5.h @@ -15,20 +15,20 @@ /** Maximum SPD size supported */ #define SPD_SIZE_MAX_DDR5 1024 -enum ddr5_module_type { - DDR5_SPD_RDIMM = 0x01, - DDR5_SPD_UDIMM = 0x02, - DDR5_SPD_SODIMM = 0x03, - DDR5_SPD_LRDIMM = 0x04, - DDR5_SPD_MINI_RDIMM = 0x05, - DDR5_SPD_MINI_UDIMM = 0x06, - DDR5_SPD_72B_SO_UDIMM = 0x08, - DDR5_SPD_72B_SO_RDIMM = 0x09, - DDR5_SPD_SOLDERED_DOWN = 0x0b, - DDR5_SPD_16B_SO_DIMM = 0x0c, - DDR5_SPD_32B_SO_RDIMM = 0x0d, - DDR5_SPD_1DPC = 0x0e, - DDR5_SPD_2DPC = 0x0f, +enum spd_dimm_type_ddr5 { + SPD_DDR5_DIMM_TYPE_RDIMM = 0x01, + SPD_DDR5_DIMM_TYPE_UDIMM = 0x02, + SPD_DDR5_DIMM_TYPE_SODIMM = 0x03, + SPD_DDR5_DIMM_TYPE_LRDIMM = 0x04, + SPD_DDR5_DIMM_TYPE_MINI_RDIMM = 0x05, + SPD_DDR5_DIMM_TYPE_MINI_UDIMM = 0x06, + SPD_DDR5_DIMM_TYPE_72B_SO_UDIMM = 0x08, + SPD_DDR5_DIMM_TYPE_72B_SO_RDIMM = 0x09, + SPD_DDR5_DIMM_TYPE_SOLDERED_DOWN = 0x0b, + SPD_DDR5_DIMM_TYPE_16B_SO_DIMM = 0x0c, + SPD_DDR5_DIMM_TYPE_32B_SO_RDIMM = 0x0d, + SPD_DDR5_DIMM_TYPE_1DPC = 0x0e, + SPD_DDR5_DIMM_TYPE_2DPC = 0x0f, }; /** |