diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb | 33 |
1 files changed, 15 insertions, 18 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index ac3ebdcbf8..c3930196c2 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -1,33 +1,30 @@ chip soc/intel/alderlake - # FSP Memory - register "enable_c6dram" = "1" - register "sagv" = "SaGv_Enabled" - - # FSP Silicon - register "eist_enable" = "1" - register "enable_c1e" = "1" - - register "disable_dynamic_tccold_handshake" = "1" + # FSP UPDs + register "disable_dynamic_tccold_handshake" = "true" + register "eist_enable" = "true" + register "enable_c1e" = "true" + register "enable_c6dram" = "true" + register "sagv" = "SaGv_Enabled" # Serial I/O register "serial_io_i2c_mode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C0] = PchSerialIoPci, }" register "serial_io_uart_mode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, }" # Power - register "pch_slp_s3_min_assertion_width" = "2" # 50ms - register "pch_slp_s4_min_assertion_width" = "3" # 1s - register "pch_slp_sus_min_assertion_width" = "3" # 500ms - register "pch_slp_a_min_assertion_width" = "3" # 2s + register "pch_slp_s3_min_assertion_width" = "2" # 50ms + register "pch_slp_s4_min_assertion_width" = "3" # 1s + register "pch_slp_sus_min_assertion_width" = "3" # 500ms + register "pch_slp_a_min_assertion_width" = "3" # 2s # PM Util - register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_C" - register "pmc_gpe0_dw2" = "GPP_E" + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_C" + register "pmc_gpe0_dw2" = "GPP_E" # Device Tree device domain 0 on |