9 files changed, 56 insertions, 21 deletions
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index ab0cf8ab6e..ca2f7b36ee 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -10,6 +10,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
 	select SSE
 	select UDELAY_TSC
 	select SIPI_VECTOR_IN_ROM
+	select C_ENVIRONMENT_BOOTBLOCK
 
 # mPGA604 are usually Intel Netburst CPUs which should have SSE2
 # but the ramtest.c code on the Dell S1850 seems to choke on
@@ -26,4 +27,8 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x4000
 
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x2000
+
 endif # CPU_INTEL_SOCKET_MPGA604
diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc
index 371f7a6b6b..9e3b8d75bf 100644
--- a/src/cpu/intel/socket_mPGA604/Makefile.inc
+++ b/src/cpu/intel/socket_mPGA604/Makefile.inc
@@ -7,6 +7,8 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
+bootblock-y += ../car/p4-netburst/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
+
 postcar-y += ../car/p4-netburst/exit_car.S
 romstage-y += ../car/romstage.c
diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig
index 85c45d51f3..3a729ce17a 100644
--- a/src/mainboard/aopen/dxplplusu/Kconfig
+++ b/src/mainboard/aopen/dxplplusu/Kconfig
@@ -29,6 +29,10 @@ config MAX_CPUS
 	int
 	default 4
 
+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0x4000
+
 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 	hex
 	default 0x0
diff --git a/src/mainboard/aopen/dxplplusu/Makefile.inc b/src/mainboard/aopen/dxplplusu/Makefile.inc
new file mode 100644
index 0000000000..0fedf5ce8c
--- /dev/null
+++ b/src/mainboard/aopen/dxplplusu/Makefile.inc
@@ -0,0 +1,14 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += bootblock.c
diff --git a/src/mainboard/aopen/dxplplusu/bootblock.c b/src/mainboard/aopen/dxplplusu/bootblock.c
new file mode 100644
index 0000000000..f06f76e0ad
--- /dev/null
+++ b/src/mainboard/aopen/dxplplusu/bootblock.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Kyösti Mälkki <kyosti.malkki@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <device/pnp_def.h>
+#include <superio/smsc/lpc47m10x/lpc47m10x.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1)
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Get the serial port configured. */
+	lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c
index f95c7f91e2..57538d6f80 100644
--- a/src/mainboard/aopen/dxplplusu/romstage.c
+++ b/src/mainboard/aopen/dxplplusu/romstage.c
@@ -14,22 +14,14 @@
  */
 
 #include <stdint.h>
-#include <device/pci_def.h>
 #include <arch/io.h>
-#include <stdlib.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 
 #include <southbridge/intel/i82801dx/i82801dx.h>
 #include <northbridge/intel/e7505/raminit.h>
 
-#include <device/pnp_def.h>
-#include <superio/smsc/lpc47m10x/lpc47m10x.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1)
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
@@ -46,13 +38,6 @@ void mainboard_romstage_entry(unsigned long bist)
 		},
 	};
 
-	/* Get the serial port running and print a welcome banner */
-	lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	/* If this is a warm boot, some initialization can be skipped */
 	if (!e7505_mch_is_ready()) {
 		enable_smbus();
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig
index 5670e162cf..12640b32a2 100644
--- a/src/southbridge/intel/i82801dx/Kconfig
+++ b/src/southbridge/intel/i82801dx/Kconfig
@@ -31,8 +31,4 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/intel/i82801dx/bootblock.c"
-
 endif
diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc
index 7d87995259..5ba21309d6 100644
--- a/src/southbridge/intel/i82801dx/Makefile.inc
+++ b/src/southbridge/intel/i82801dx/Makefile.inc
@@ -30,4 +30,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 romstage-y += early_smbus.c
 
+bootblock-y += bootblock.c
+
 endif
diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c
index 8ae419dd9b..a5e48e5ded 100644
--- a/src/southbridge/intel/i82801dx/bootblock.c
+++ b/src/southbridge/intel/i82801dx/bootblock.c
@@ -11,9 +11,10 @@
  * GNU General Public License for more details.
  */
 
+#include <cpu/intel/car/bootblock.h>
 #include <arch/io.h>
 
-static void bootblock_southbridge_init(void)
+void bootblock_early_southbridge_init(void)
 {
 	/* Set FWH IDs for 2 MB flash part. */
 	if (CONFIG_ROM_SIZE == 0x200000)