aboutsummaryrefslogtreecommitdiff
path: root/src/vendorcode
diff options
context:
space:
mode:
Diffstat (limited to 'src/vendorcode')
-rw-r--r--src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h19
1 files changed, 18 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
index 86fe800a2a..9aa9cbd16a 100644
--- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
@@ -65,6 +65,23 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
NULL
};
+/* The default fixed MTRR values to be set after memory initialization */
+static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
+ { CPU_LIST_TERMINAL },
+};
+
/* Process solution defined socket / family installations
*
* As part of the release package for each image, define the options below to select the
@@ -1079,7 +1096,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
#define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
#else
- #define CFG_AP_MTRR_SETTINGS_LIST (NULL)
+ #define CFG_AP_MTRR_SETTINGS_LIST (&OntarioApMtrrSettingsList)
#endif
/*---------------------------------------------------------------------------