diff options
Diffstat (limited to 'src/vendorcode/intel/fsp')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h | 317 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h | 36 |
2 files changed, 261 insertions, 92 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h index 48225e0779..d2d2461fc4 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h @@ -148,9 +148,11 @@ typedef struct { UINT8 PrimaryVideoAdaptor; /** Offset 0x004D - Package - NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L - is being used. 0x00(Default). - 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD + NOTE: Specifies CA Mapping for all technologies. Supported CA Mappings: 0 - SODIMM(Default); + 1 - BGA; 2 - BGA mirrored (LPDDR3 only); 3 - SODIMM/UDIMM with Rank 1 Mirrored + (DDR3L); Refer to the IAFW spec for specific details about each CA mapping. + 0x0:SODIMM, 0x1:BGA, 0x2:BGA mirrored (LPDDR3 only), 0x3:SODIMM/UDIMM with Rank + 1 Mirrored (DDR3L) **/ UINT8 Package; @@ -178,41 +180,54 @@ typedef struct { UINT8 MemoryDown; /** Offset 0x0050 - DDR3LPageSize - NOTE: Only for memory down or downgrade DDR3L frequency. 0x01:1KB(Default), 0x02:2KB. + NOTE: Only for memory down (soldered down memory with no SPD). 0x01:1KB(Default), 0x02:2KB. 0x1:1KB, 0x2:2KB **/ UINT8 DDR3LPageSize; /** Offset 0x0051 - DDR3LASR - NOTE: Only for memory down. 0x00:Not Supported(Default), 0x01:Supported. + NOTE: Only for memory down. This is specific to ddr3l and used for refresh adjustment + in Self Refresh, does not affect LP4. 0x00:Not Supported(Default), 0x01:Supported. 0x0:Not Supported, 0x1:Supported **/ UINT8 DDR3LASR; /** Offset 0x0052 - ScramblerSupport - Scrambler Support. 0x00:Not Supported, 0x01:Supported(Default). + Scrambler Support - Enable or disable the memory scrambler. Data scrambling is + provided as a means to increase signal integrity/reduce RFI generated by the DRAM + interface. This is achieved by randomizing seed that encodes/decodes memory data + so repeating a worse case pattern is hard to repeat. 00: Disable Scrambler Support, + 01: Enable Scrambler Support $EN_DIS **/ UINT8 ScramblerSupport; /** Offset 0x0053 - ChannelHashMask - Channel Hash Mask. 0x00(Default). + ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be + modified. These inputs are not used for configurations where an optimized ChannelHashMask + has been provided by the PnP validation teams. 0x00(Default). **/ UINT16 ChannelHashMask; /** Offset 0x0055 - SliceHashMask - Slice Hash Mask. 0x00(Default). + ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be + modified. These inputs are not used for configurations where an optimized ChannelHashMask + has been provided by the PnP validation teams. 0x00(Default). **/ UINT16 SliceHashMask; /** Offset 0x0057 - InterleavedMode - Interleaved Mode. 0x00:Disable(Default), 0x02:Enable. + This field is ignored if one of the PnP channel configurations is used. If the memory + configuration is different, then the field is used directly to populate. 0x00:Disable(Default), + 0x02:Enable. 0x0:Disable, 0x2:Enable **/ UINT8 InterleavedMode; /** Offset 0x0058 - ChannelsSlicesEnable - Channels Slices Enable. 0x00:Disable(Default), 0x01:Enable. + ChannelSlicesEnable field is not used at all on BXTP. The Channel Slice Configuration + is calculated internally based on the enabled channel configuration. 0x00:Disable(Default), + 0x01:Enable. $EN_DIS **/ UINT8 ChannelsSlicesEnable; @@ -231,8 +246,8 @@ typedef struct { UINT8 DualRankSupportEnable; /** Offset 0x005B - RmtMode - Rank Margin Tool Mode. 0x00(Default). - $EN_DIS + Rank Margin Tool Mode. 0x00(Default), 0x3(Enabled). + 0x0:Disabled, 0x3:Enabled **/ UINT8 RmtMode; @@ -251,8 +266,8 @@ typedef struct { UINT16 LowMemoryMaxValue; /** Offset 0x0060 - DisableFastBoot - 00:Disabled Used saved training data (if valid)(Default), 01:Enabled; Full re-train - of memory. + 00:Disabled; Use saved training data (if valid) after first boot(Default), 01:Enabled; + Full re-train of memory on every boot. $EN_DIS **/ UINT8 DisableFastBoot; @@ -275,209 +290,325 @@ typedef struct { UINT8 DIMM1SPDAddress; /** Offset 0x0065 - Ch0_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch0 rank. 0x00(Default). + NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. + NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank + 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be + set to 1 to enable use of this rank. **/ UINT8 Ch0_RankEnable; /** Offset 0x0066 - Ch0_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). + NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel + (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 + and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 + device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ UINT8 Ch0_DeviceWidth; /** Offset 0x0067 - Ch0_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). + NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device + density per rank (per Chip Select). The simplest way of identifying the density + per rank is to divide the total SoC memory channel density by the number of ranks. + For DDR3L: Must specify the DRAM device density per DRAM device. For example, an + 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, + a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - + 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ UINT8 Ch0_DramDensity; /** Offset 0x0068 - Ch0_Option - Rank Select Interleaving Enable. See Address Mapping section for full description. - 0:Rank Select Interleaving disabled, 1:Rank Select Interleaving enabled. [1] Bank - Address Hashing Enable. See Address Mapping section for full description. 0:Bank - Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] - This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B). - 0x03(Default). + BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: + 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] + Bank Address Hashing Enable. See Address Mapping section for full description: + 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 + CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board + designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 + CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register + specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) **/ UINT8 Ch0_Option; /** Offset 0x0069 - Ch0_OdtConfig - ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. + [0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination + during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120 + OHMS or so roughly. Purpose: Save power on these technologies which burn power + directly proportional to ODT strength, because ODT looks like a PU and PD (e.g. + a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG, + 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The + customer needs to choose this based on their actual board strapping (how they tie + the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW + ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24, + which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS + signals). Purpose: To improve signal integrity and provide a much more optimized + CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default), + 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only: + 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120 + Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care **/ UINT8 Ch0_OdtConfig; /** Offset 0x006A - Ch0_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). + Not used **/ UINT8 Ch0_TristateClk1; /** Offset 0x006B - Ch0_Mode2N - 2N Mode. 0x00(Default). + DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command + mode that provides more setup and hold time for DRAM commands on the DRAM command + bus. This is useful for platforms with unusual CMD bus routing or marginal signal + integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and + Control training), 1 - Force 2N Mode + 0x0:Auto, 0x1:Force 2N CMD Timing Mode **/ UINT8 Ch0_Mode2N; /** Offset 0x006C - Ch0_OdtLevels - Rank Select Interleaving Enable. See Address Mapping section for full description. - 0:Rank Select Interleaving disabled(Default), 1:Rank Select Interleaving enabled. - [1] Bank Address Hashing Enable. See Address Mapping section for full description. - 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used:00:1KB (A), 01:2KB (B). + Parameter used to determine if ODT will be held high or low: 0 - ODT Connected to + SoC, 1 - ODT held high **/ UINT8 Ch0_OdtLevels; /** Offset 0x006D - Ch1_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch1 rank. + NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. + NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank + 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be + set to 1 to enable use of this rank. **/ UINT8 Ch1_RankEnable; /** Offset 0x006E - Ch1_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). + NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel + (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 + and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 + device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ UINT8 Ch1_DeviceWidth; /** Offset 0x006F - Ch1_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default). + NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device + density per rank (per Chip Select). The simplest way of identifying the density + per rank is to divide the total SoC memory channel density by the number of ranks. + For DDR3L: Must specify the DRAM device density per DRAM device. For example, an + 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, + a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - + 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ UINT8 Ch1_DramDensity; /** Offset 0x0070 - Ch1_Option - Rank Select Interleaving Enable. See Address Mapping section for full description. - 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] - Bank Address Hashing Enable. See Address Mapping section for full description. - 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB - (B), 0x03(Default). + BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: + 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] + Bank Address Hashing Enable. See Address Mapping section for full description: + 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 + CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board + designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 + CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register + specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) **/ UINT8 Ch1_Option; /** Offset 0x0071 - Ch1_OdtConfig - ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. + BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG; + LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS, + 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4: + X = Don't Care **/ UINT8 Ch1_OdtConfig; /** Offset 0x0072 - Ch1_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). + Not used **/ UINT8 Ch1_TristateClk1; /** Offset 0x0073 - Ch1_Mode2N - 2N Mode. 0x00(Default). + DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command + mode that provides more setup and hold time for DRAM commands on the DRAM command + bus. This is useful for platforms with unusual CMD bus routing or marginal signal + integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and + Control training), 1 - Force 2N Mode + 0x0:Auto, 0x1:Force 2N CMD Timing Mode **/ UINT8 Ch1_Mode2N; /** Offset 0x0074 - Ch1_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), - 1:ODT_AB_HIGH_HIGH. 3:ODT_AB_HIGH_LOW. + DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW + (default), 1 - ODT_AB_HIGH_HIGH **/ UINT8 Ch1_OdtLevels; /** Offset 0x0075 - Ch2_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch2 rank. + NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. + NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank + 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be + set to 1 to enable use of this rank. **/ UINT8 Ch2_RankEnable; /** Offset 0x0076 - Ch2_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. + NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel + (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 + and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 + device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ UINT8 Ch2_DeviceWidth; /** Offset 0x0077 - Ch2_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). + NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device + density per rank (per Chip Select). The simplest way of identifying the density + per rank is to divide the total SoC memory channel density by the number of ranks. + For DDR3L: Must specify the DRAM device density per DRAM device. For example, an + 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, + a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - + 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ UINT8 Ch2_DramDensity; /** Offset 0x0078 - Ch2_Option - Rank Select Interleaving Enable. See Address Mapping section for full description.. - 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] - Bank Address Hashing Enable. See Address Mapping section for full description.. - 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used:. 00:1KB (A)(Default). - 01:2KB (B). + BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: + 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] + Bank Address Hashing Enable. See Address Mapping section for full description: + 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 + CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board + designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 + CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register + specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) **/ UINT8 Ch2_Option; /** Offset 0x0079 - Ch2_OdtConfig - ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. + BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG; + LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS, + 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4: + X = Don't Care **/ UINT8 Ch2_OdtConfig; /** Offset 0x007A - Ch2_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). + Not used **/ UINT8 Ch2_TristateClk1; /** Offset 0x007B - Ch2_Mode2N - 2N Mode. 0x00(Default). + DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command + mode that provides more setup and hold time for DRAM commands on the DRAM command + bus. This is useful for platforms with unusual CMD bus routing or marginal signal + integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and + Control training), 1 - Force 2N Mode + 0x0:Auto, 0x1:Force 2N CMD Timing Mode **/ UINT8 Ch2_Mode2N; /** Offset 0x007C - Ch2_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), - 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. + DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW + (default), 1 - ODT_AB_HIGH_HIGH **/ UINT8 Ch2_OdtLevels; /** Offset 0x007D - Ch3_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch3 rank. 0x00(Default). + NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. + NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank + 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be + set to 1 to enable use of this rank. **/ UINT8 Ch3_RankEnable; /** Offset 0x007E - Ch3_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00:x8(Default), - 0x01:x16, 0x02:x32, 0x03:x64. + NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel + (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 + and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 + device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ UINT8 Ch3_DeviceWidth; /** Offset 0x007F - Ch3_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default), - 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb. + NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device + density per rank (per Chip Select). The simplest way of identifying the density + per rank is to divide the total SoC memory channel density by the number of ranks. + For DDR3L: Must specify the DRAM device density per DRAM device. For example, an + 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, + a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - + 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ UINT8 Ch3_DramDensity; /** Offset 0x0080 - Ch3_Option - Rank Select Interleaving Enable. See Address Mapping section for full description.. - 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] - Bank Address Hashing Enable. See Address Mapping section for full description.. - 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used:. 00 - 1KB (A). 01 - - 2KB (B). + BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: + 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] + Bank Address Hashing Enable. See Address Mapping section for full description: + 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 + CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board + designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 + CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register + specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) **/ UINT8 Ch3_Option; /** Offset 0x0081 - Ch3_OdtConfig - ODT configuration control.. 0:WEAK_ODT_CONFIG(Default). 1:STRONG_ODT_CONFIG. + BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG; + LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS, + 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4: + X = Don't Care **/ UINT8 Ch3_OdtConfig; /** Offset 0x0082 - Ch3_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). + Not used **/ UINT8 Ch3_TristateClk1; /** Offset 0x0083 - Ch3_Mode2N - 2N Mode. 0x00(Default). + DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command + mode that provides more setup and hold time for DRAM commands on the DRAM command + bus. This is useful for platforms with unusual CMD bus routing or marginal signal + integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and + Control training), 1 - Force 2N Mode + 0x0:Auto, 0x1:Force 2N CMD Timing Mode **/ UINT8 Ch3_Mode2N; /** Offset 0x0084 - Ch3_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), - 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. + DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW + (default), 1 - ODT_AB_HIGH_HIGH **/ UINT8 Ch3_OdtLevels; /** Offset 0x0085 - RmtCheckRun - RmtCheckRun: 0x00(Default). + Parameter used to determine whether to run the margin check. Bit 0 is used for MINIMUM + MARGIN CHECK and bit 1 is used for DEGRADE MARGIN CHECK **/ UINT8 RmtCheckRun; /** Offset 0x0086 - Ch0_Bit_swizzling - Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. + Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. Frequently + asked questions: Q: The DQS (strobes) need to go with the corresponding byte lanes + on the DDR module. Are the DQS being swapped around as well? Ans: Yes, DQ strobes + need to follow the DQ byte lane they correspond too. So for example if you have + DQ[7:0] swapped with DQ[15:8], DQS0 pair also need to be swapped with DQS1 pair. + Also, the spreadsheet used for Amenia is essentially a swizzle value lookup that + specifies what DRAM DQ bit a particular SoC DQ bit is connected to. Some confusion + can arrise from the fact that the indexes to the array do not necessarily map 1:1 + to an SoC DQ pin. For example, the CH0 array at index 0 maps to SoC DQB8. The value + of 9 at index 0 tells us that SoC DQB8 is connected to DRAM DQA9. Q: The PDG indicates + a 2 physical channels need to be stuffed and operated together. Are the CHx_A and + CHx_B physical channels operated in tandem or completely separate? If separate, + why requirement of pairing them? Ans: We have 2 PHY instances on the SoC each supporting + up to 2 x32 LP4 channels. If you have 4 channels both PHYs are active, but if you + have 2 channels in order to power gate one PHY, those two channel populated must + be on one PHY instance. So yes all channels are independent of each other, but + there are some restrictions on how they need to be populated. Q: How is it that + an LPDDR4 device is identified as having a x16 width when all 32-bits are used + at the same time with a single chip select? That's effectively a x32 device. Ans:LPDDR4 + DRAM devices are x16. Each die has 2 x16 devices on them. To make a x32 channel + the CS of the two devices in the same die are connected together to make a single + rank of one x32 channel (SDP). The second die in the DDP package makes the second rank. **/ UINT8 Ch0_Bit_swizzling[32]; @@ -497,12 +628,12 @@ typedef struct { UINT8 Ch3_Bit_swizzling[32]; /** Offset 0x0106 - RmtMarginCheckScaleHighThreshold - RmtMarginCheckScaleHighThreshold. 0x0000(Default). + Percentage used to determine the margin tolerances over the failing margin. **/ UINT16 RmtMarginCheckScaleHighThreshold; /** Offset 0x0108 - MsgLevelMask - MsgLevelMask. 0x00000000(Default). + 32 bits used to mask out debug messages. Masking out bit 0 mask all other messages. **/ UINT32 MsgLevelMask; @@ -651,14 +782,34 @@ typedef struct { UINT8 SwTraceEn; /** Offset 0x014A - Periodic Retraining Disable - Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS + Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic + Retraining for debug purposes. Periodic Retraining should be enabled in production. + Periodic retraining allows the platform to operate reliably over a larger voltage + and temperature range. This field has no effect for DDR3L and LPDDR3 memory type + configurations. 0x00: Enable Periodic Retraining (default); 0x01: Disable Periodic + Retraining (debug configuration only) + 0x0:Enabled, 0x1:Disabled **/ UINT8 PeriodicRetrainingDisable; -/** Offset 0x014B +/** Offset 0x014B - Enable Reset System + Enable FSP to trigger reset instead of returning reset request. 0x00: Return the + Return Status from FSP if a reset is required. (default); 0x01: Perform Reset inside + FSP instead of returning from the API. + 0x0:Disabled, 0x1:Enabled +**/ + UINT8 EnableResetSystem; + +/** Offset 0x014C - Enable HECI2 in S3 resume path + Enable HECI2 in S3 resume path. 0x00: Skip HECI2 initialization in S3 resume. ; + 0x01: Enable HECI2 in S3 resume path.(Default) + 0x0:Disabled, 0x1:Enabled +**/ + UINT8 EnableS3Heci2; + +/** Offset 0x014D **/ - UINT8 ReservedFspmUpd[5]; + UINT8 ReservedFspmUpd[3]; } FSP_M_CONFIG; /** Fsp M Test Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h index 553eba3f18..311980774b 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h @@ -530,6 +530,7 @@ typedef struct { /** Offset 0x009F - HD-Audio BIOS Configuration Lock Down Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. + This option is deprecated $EN_DIS **/ UINT8 BiosCfgLockDown; @@ -1480,20 +1481,37 @@ typedef struct { **/ UINT8 MonitorMwaitEnable; -/** Offset 0x0328 +/** Offset 0x0328 - IRQ Interrupt Polarity Control + Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low **/ - UINT8 ReservedFspsUpd[8]; + UINT32 IPC[4]; + +/** Offset 0x0338 - Disable ModPHY dynamic power gate + Disable ModPHY dynamic power gate for the specific SATA port. +**/ + UINT8 SataPortsDisableDynamicPg[2]; + +/** Offset 0x033A - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 HdAudioDspUaaCompliance; + +/** Offset 0x033B +**/ + UINT8 ReservedFspsUpd[5]; } FSP_S_CONFIG; /** Fsp S Test Configuration **/ typedef struct { -/** Offset 0x0330 +/** Offset 0x0340 **/ UINT32 Signature; -/** Offset 0x0334 +/** Offset 0x0344 **/ UINT8 ReservedFspsTestUpd[12]; } FSP_S_TEST_CONFIG; @@ -1502,11 +1520,11 @@ typedef struct { **/ typedef struct { -/** Offset 0x0340 +/** Offset 0x0350 **/ UINT32 Signature; -/** Offset 0x0344 +/** Offset 0x0354 **/ UINT8 ReservedFspsRestrictedUpd[12]; } FSP_S_RESTRICTED_CONFIG; @@ -1523,15 +1541,15 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0330 +/** Offset 0x0340 **/ FSP_S_TEST_CONFIG FspsTestConfig; -/** Offset 0x0340 +/** Offset 0x0350 **/ FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; -/** Offset 0x0350 +/** Offset 0x0360 **/ UINT16 UpdTerminator; } FSPS_UPD; |