diff options
Diffstat (limited to 'src/vendorcode/intel/fsp1_0/rangeley/include')
5 files changed, 179 insertions, 7 deletions
diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h new file mode 100644 index 0000000000..b9a6183d73 --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h @@ -0,0 +1,69 @@ +/** @file + +Copyright (C) 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#ifndef __FSP_GUID_H__ +#define __FSP_GUID_H__ + +/** + + FSP specific GUID HOB definitions + + **/ +#define FSP_INFO_HEADER_GUID \ + { \ + 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ + } + +#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ + { \ + 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \ + } + +#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ + { \ + 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \ + } + +#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ + { \ + 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \ + } + +#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ + { \ + 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \ + } + +#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ + { \ + 0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \ + } + +#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h index ce479bf9f8..c35dca0c96 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h @@ -1,6 +1,6 @@ /** -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013 - 2015, Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -74,6 +74,7 @@ typedef struct { UINT8 tRTPmin; // 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) UINT8 UpperNibbleFortFAW; // 28 Upper Nibble for tFAW UINT8 tFAWmin; // 29 Minimum Four Activate Window Delay Time (tFAWmin) + UINT8 SdramThermalRefreshOption; // 31 SdramThermalRefreshOption UINT8 ModuleThermalSensor; // 32 ModuleThermalSensor UINT8 SDRAMDeviceType; // 33 SDRAM Device Type UINT8 tCKminFine; // 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h new file mode 100644 index 0000000000..dbbbf779dc --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h @@ -0,0 +1,95 @@ +/** @file + +Copyright (C) 2013 - 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#ifndef __FSP_SUPPORT_H__ +#define __FSP_SUPPORT_H__ + +#include "fsptypes.h" +#include "fspfv.h" +#include "fspffs.h" +#include "fspapi.h" +#include "fsphob.h" +#include "fspguid.h" +#include "fspplatform.h" +#include "fspinfoheader.h" +#include "fspbootmode.h" +#include "fspvpd.h" + +UINT32 +GetUsableLowMemTop ( + CONST VOID *HobListPtr + ); + +UINT64 +GetUsableHighMemTop ( + CONST VOID *HobListPtr + ); + +VOID * +GetGuidHobDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length, + EFI_GUID *Guid + ); + +VOID +GetFspReservedMemoryFromGuid ( + CONST VOID *HobListPtr, + EFI_PHYSICAL_ADDRESS *FspMemoryBase, + UINT64 *FspMemoryLength, + EFI_GUID *FspReservedMemoryGuid + ); + +UINT32 +GetTsegReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +); + +UINT32 +GetFspReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +); + +VOID* +GetFspNvsDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length + ); + +VOID * +GetBootloaderTempMemoryBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length + ); + + +#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h index 5912e0115b..da19250632 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h @@ -100,13 +100,18 @@ typedef struct { #define TRUE ((BOOLEAN)(1==1)) #define FALSE ((BOOLEAN)(0==1)) +static inline void DebugDeadLoop(void) { + for (;;); +} + #define FSPAPI __attribute__((cdecl)) #define EFIAPI __attribute__((cdecl)) +#define _ASSERT(Expression) DebugDeadLoop() #define ASSERT(Expression) \ do { \ if (!(Expression)) { \ - for (;;); \ + _ASSERT (Expression); \ } \ } while (FALSE) diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h index fba38a0e25..4ba1a28cfa 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2013-2014 Intel Corporation +Copyright (C) 2015, Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -50,7 +50,8 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdSpdBaseAddress_0_1; /* Offset 0x0026 */ UINT8 PcdSpdBaseAddress_1_0; /* Offset 0x0027 */ UINT8 PcdSpdBaseAddress_1_1; /* Offset 0x0028 */ - UINT8 UnusedUpdSpace1[7]; /* Offset 0x0029 */ + UINT8 PcdExtendedTemperatureEnable; /* Offset 0x0029 */ + UINT8 UnusedUpdSpace1[6]; /* Offset 0x002A */ UINT8 PcdEnableLan; /* Offset 0x0030 */ UINT8 PcdEnableSata2; /* Offset 0x0031 */ UINT8 PcdEnableSata3; /* Offset 0x0032 */ @@ -65,13 +66,14 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */ UINT8 PcdFastboot; /* Offset 0x0041 */ UINT8 PcdEccSupport; /* Offset 0x0042 */ - UINT8 PcdCustomerRevision[32]; /* Offset 0x0043 */ - UINT8 UnusedUpdSpace3[13]; /* Offset 0x0063 */ + UINT8 PcdSerialPortBaudRate; /* Offset 0x0043 */ + UINT8 PcdCustomerRevision[32]; /* Offset 0x0044 */ + UINT8 UnusedUpdSpace3[12]; /* Offset 0x0064 */ UINT16 PcdRegionTerminator; /* Offset 0x0070 */ } UPD_DATA_REGION; #define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */ -#define VPD_IMAGE_REV 0x00000102 +#define VPD_IMAGE_REV 0x00000140 typedef struct _VPD_DATA_REGION { UINT64 PcdVpdRegionSign; /* Offset 0x0000 */ |