diff options
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h | 111 |
1 files changed, 84 insertions, 27 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h index 8dc2db9437..248b4d5ef1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h @@ -53,6 +53,25 @@ extern EFI_GUID gSiMemoryPlatformDataGuid; #define B_RANK2_PRS BIT4 #define B_RANK3_PRS BIT5 +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + /// /// Defines taken from MRC so avoid having to include MrcInterface.h /// @@ -122,7 +141,7 @@ typedef struct { #define MRC_DDR_TYPE_UNKNOWN 3 #endif -#define MAX_PROFILE_NUM 4 // number of memory profiles supported +#define MAX_PROFILE_NUM 4 // number of memory profiles supported #define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported // @@ -151,64 +170,102 @@ typedef struct { UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. } MRC_CH_TIMING; +typedef struct { + UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. + UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. + UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). + UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. +} MRC_TA_TIMING; + /// /// Memory SMBIOS & OC Memory Data Hob /// typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. } DIMM_INFO; typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics. + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. } CHANNEL_INFO; typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions. + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. + MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings + MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings + MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings + MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings } CONTROLLER_INFO; typedef struct { UINT8 Revision; - UINT16 DataWidth; + UINT16 DataWidth; ///< Data width, in bits, of this memory device /** As defined in SMBIOS 3.0 spec Section 7.18.2 and Table 75 **/ - UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT32 Frequency; ///< The system's common memory controller frequency in MT/s. + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) /** As defined in SMBIOS 3.0 spec Section 7.17.3 and Table 72 **/ UINT8 ErrorCorrectionType; SiMrcVersion Version; - UINT32 FreqMax; BOOLEAN EccSupport; UINT8 MemoryProfile; UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM]; // Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; // If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. UINT8 Ratio; UINT8 RefClk; UINT32 VddVoltage[MAX_PROFILE_NUM]; CONTROLLER_INFO Controller[MAX_NODE]; } MEMORY_INFO_DATA_HOB; +/** + Memory Platform Data Hob + + <b>Revision 1:</b> + - Initial version. + <b>Revision 2:</b> + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT32 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + #pragma pack (pop) #endif // _MEM_INFO_HOB_H_ |