diff options
Diffstat (limited to 'src/vendorcode/cavium/bdk')
| -rw-r--r-- | src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c | 6 | ||||
| -rw-r--r-- | src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c index a7602de758..4eeeca3dae 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c @@ -166,7 +166,7 @@ int __bdk_qlm_errata_gser_26150(bdk_node_t node, int qlm, int baud_mhz) Enable Rx power state override */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), c.s.cfg_tx_pstate_req_ovrrd_en = 0x1; - c.s.cfg_rx_pstate_req_ovrrd_en = 0X1); + c.s.cfg_rx_pstate_req_ovrrd_en = 0x1); /* Step 4: Set GSER()_LANE(lane_n)_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ] = 1 Start the CTLIFC override state machine */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), @@ -200,7 +200,7 @@ int __bdk_qlm_errata_gser_26150(bdk_node_t node, int qlm, int baud_mhz) Enable Rx power state override */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), c.s.cfg_tx_pstate_req_ovrrd_en = 0x1; - c.s.cfg_rx_pstate_req_ovrrd_en = 0X1); + c.s.cfg_rx_pstate_req_ovrrd_en = 0x1); /* Step 10: Set GSER()_LANE(lane_n)_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ] = 1 Start the CTLIFC override state machine */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), @@ -219,7 +219,7 @@ int __bdk_qlm_errata_gser_26150(bdk_node_t node, int qlm, int baud_mhz) Disable Rx power state override */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), c.s.cfg_tx_pstate_req_ovrrd_en = 0x0; - c.s.cfg_rx_pstate_req_ovrrd_en = 0X0); + c.s.cfg_rx_pstate_req_ovrrd_en = 0x0); } /* Step 13: Poll GSER()_PLL_STAT.[PLL_LOCK] = 1 Poll and check that PLL is locked */ diff --git a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c index 306678759d..92cbe74a01 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c @@ -3148,7 +3148,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node, bank_bits = (2 + ((spd_banks >> 4) & 0x3)) + ((spd_banks >> 6) & 0x3); bank_bits = min((int)bank_bits, 4); /* Controller can only address 4 bits. */ - spd_package = 0XFF & read_spd(node, &dimm_config_table[0], DDR4_SPD_PACKAGE_TYPE); + spd_package = 0xFF & read_spd(node, &dimm_config_table[0], DDR4_SPD_PACKAGE_TYPE); if (spd_package & 0x80) { // non-monolithic device is_stacked_die = (!disable_stacked_die) ? ((spd_package & 0x73) == 0x11) : 0; ddr_print("DDR4: Package Type 0x%x (%s), %d die\n", spd_package, |