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Diffstat (limited to 'src/vendorcode/amd/cimx/sb800/SBCMN.c')
-rw-r--r--src/vendorcode/amd/cimx/sb800/SBCMN.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c
index 6ae736c81c..a596036d69 100644
--- a/src/vendorcode/amd/cimx/sb800/SBCMN.c
+++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c
@@ -73,7 +73,7 @@ VOID sbUsbPhySetting (IN UINT32 Value);
* sbEarlyPostByteInitTable - PCI device registers initial during early POST.
*
*/
-REG8MASK sbEarlyPostByteInitTable[] =
+const static REG8MASK sbEarlyPostByteInitTable[] =
{
// SMBUS Device (Bus 0, Dev 20, Func 0)
{0x00, SMBUS_BUS_DEV_FUN, 0},
@@ -124,7 +124,7 @@ REG8MASK sbEarlyPostByteInitTable[] =
* sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST.
*
*/
-AcpiRegWrite sbPmioEPostInitTable[] =
+const static AcpiRegWrite sbPmioEPostInitTable[] =
{
// HPET workaround
{PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},
@@ -241,7 +241,7 @@ AcpiRegWrite sbPmioEPostInitTable[] =
* abTblEntry800 - AB-Link Configuration Table for SB800
*
*/
-ABTBLENTRY abTblEntry800[] =
+const static ABTBLENTRY abTblEntry800[] =
{
// RPR Enable downstream posted transactions to pass non-posted transactions.
{ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},
@@ -287,7 +287,7 @@ ABTBLENTRY abTblEntry800[] =
* SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature
*
*/
-ABTBLENTRY SbPcieOrderRule[] =
+const static ABTBLENTRY SbPcieOrderRule[] =
{
// abPostPassNpDownStreamTbl
{ABCFG, SB_ABCFG_REG10060, BIT31, BIT31},