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-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/Makefile.inc32
1 files changed, 32 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/Makefile.inc
new file mode 100644
index 0000000000..f28c5f7d09
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/Makefile.inc
@@ -0,0 +1,32 @@
+libagesa-y += F15OrC6State.c
+libagesa-y += F15OrCpb.c
+libagesa-y += F15OrEarlySamples.c
+libagesa-y += F15OrEquivalenceTable.c
+libagesa-y += F15OrHtPhyTables.c
+libagesa-y += F15OrInitEarlyTable.c
+libagesa-y += F15OrIoCstate.c
+libagesa-y += F15OrL3Features.c
+libagesa-y += F15OrLogicalIdTables.c
+libagesa-y += F15OrLowPwrPstate.c
+libagesa-y += F15OrMicrocodePatch06000425.c
+libagesa-y += F15OrMicrocodePatch0600050D_Enc.c
+libagesa-y += F15OrMicrocodePatch06000624_Enc.c
+libagesa-y += F15OrMicrocodePatchTables.c
+libagesa-y += F15OrMsgBasedC1e.c
+libagesa-y += F15OrMsrTables.c
+libagesa-y += F15OrMultiLinkPciTables.c
+libagesa-y += F15OrPciTables.c
+libagesa-y += F15OrPmNbCofVidInit.c
+libagesa-y += F15OrPowerMgmtSystemTables.c
+libagesa-y += F15OrPowerPlane.c
+libagesa-y += F15OrSharedMsrTable.c
+libagesa-y += F15OrSingleLinkPciTables.c
+libagesa-y += F15OrUtilities.c
+libagesa-y += F15OrWorkaroundsTable.c
+libagesa-y += cpuF15OrCacheFlushOnHalt.c
+libagesa-y += cpuF15OrCoreAfterReset.c
+libagesa-y += cpuF15OrDmi.c
+libagesa-y += cpuF15OrFeatureLeveling.c
+libagesa-y += cpuF15OrNbAfterReset.c
+libagesa-y += cpuF15OrPstate.c
+libagesa-y += cpuF15OrSoftwareThermal.c