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-rwxr-xr-xsrc/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h
index b29afa6892..c8a4c9b910 100755
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h
@@ -74,9 +74,6 @@
//#define PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000)
//#define PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000)
-#define IS_LAST_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) == 0) : (1==1))
-#define IS_VALID_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : (1==0))
-
// Get lowest PHY lane on engine
#define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0xFF)
// Get highest PHY lane on engine