diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/Legacy')
| -rw-r--r-- | src/vendorcode/amd/agesa/Legacy/PlatformMemoryConfiguration.inc | 402 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/Legacy/Proc/Dispatcher.c | 161 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/Legacy/Proc/Legacy.bat | 286 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/Legacy/Proc/agesaCallouts.c | 397 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/Legacy/Proc/arch2008.asm | 2674 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/Legacy/Proc/hobTransfer.c | 394 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/Legacy/agesa.inc | 2547 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/Legacy/amd.inc | 461 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/Legacy/bridge32.inc | 577 |
9 files changed, 0 insertions, 7899 deletions
diff --git a/src/vendorcode/amd/agesa/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/Legacy/PlatformMemoryConfiguration.inc deleted file mode 100644 index 86643230ea..0000000000 --- a/src/vendorcode/amd/agesa/Legacy/PlatformMemoryConfiguration.inc +++ /dev/null @@ -1,402 +0,0 @@ -; **************************************************************************** -; * -; * @file -; * -; * AMD Platform Specific Memory Configuration -; * -; * Contains AMD AGESA Memory Configuration Override Interface -; * -; * @xrefitem bom "File Content Label" "Release Content" -; * @e project: AGESA -; * @e sub-project: Include -; * @e \$Revision: 22910 $ @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $ -; -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** - -IFNDEF PSO_ENTRY - PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry -ENDIF -; ***************************************************************************************** -; * -; * PLATFORM SPECIFIC MEMORY DEFINITIONS -; * -; ***************************************************************************************** -; */ -; -; < Memory Speed and DIMM Population Masks -; -; < DDR Speed Masks -; -ANY_SPEED EQU 0FFFFFFFFh -DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66)) -DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66)) -DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66)) -DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66)) -DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66)) -DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66)) -DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66)) -DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66)) -; < -; < DIMM POPULATION MASKS -; -ANY_ EQU 0FFh -SR_DIMM0 EQU 0001h -SR_DIMM1 EQU 0010h -SR_DIMM2 EQU 0100h -SR_DIMM3 EQU 1000h -DR_DIMM0 EQU 0002h -DR_DIMM1 EQU 0020h -DR_DIMM2 EQU 0200h -DR_DIMM3 EQU 2000h -QR_DIMM0 EQU 0004h -QR_DIMM1 EQU 0040h -QR_DIMM2 EQU 0400h -QR_DIMM3 EQU 4000h -ANY_DIMM0 EQU 000Fh -ANY_DIMM1 EQU 00F0h -ANY_DIMM2 EQU 0F00h -ANY_DIMM3 EQU 0F000h -; -; Number of Dimms -; -ANY_NUM EQU 0FFh -NO_DIMM EQU 00h -ONE_DIMM EQU 01h -TWO_DIMM EQU 02h -THREE_DIMM EQU 04h -FOUR_DIMM EQU 08h -; ***************************************************************************************** -; * -; * Platform Specific Override Definitions for Socket, Channel and Dimm -; * This indicates where a platform override will be applied. -; * -; ***************************************************************************************** -; -; SOCKET MASKS -; -ANY_SOCKET EQU 0FFh -SOCKET0 EQU 01h -SOCKET1 EQU 02h -SOCKET2 EQU 04h -SOCKET3 EQU 08h -SOCKET4 EQU 10h -SOCKET5 EQU 20h -SOCKET6 EQU 40h -SOCKET7 EQU 80h -; -; CHANNEL MASKS -; -ANY_CHANNEL EQU 0FFh -CHANNEL_A EQU 01h -CHANNEL_B EQU 02h -CHANNEL_C EQU 04h -CHANNEL_D EQU 08h -; -; DIMM MASKS -; -ALL_DIMMS EQU 0FFh -DIMM0 EQU 01h -DIMM1 EQU 02h -DIMM2 EQU 04h -DIMM3 EQU 08h -; -; REGISTER ACCESS MASKS -; -ACCESS_NB0 EQU 0h -ACCESS_NB1 EQU 01h -ACCESS_NB2 EQU 02h -ACCESS_NB3 EQU 03h -ACCESS_NB4 EQU 04h -ACCESS_PHY EQU 05h -ACCESS_DCT_XT EQU 06h -; ***************************************************************************************** -; * -; * Platform Specific Overriding Table Definitions -; * -; ***************************************************************************************** -PSO_END EQU 0 ; < Table End -PSO_CKE_TRI EQU 1 ; < CKE Tristate Map -PSO_ODT_TRI EQU 2 ; < ODT Tristate Map -PSO_CS_TRI EQU 3 ; < CS Tristate Map -PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel -PSO_CLK_SPEED EQU 5 ; < Clock Speed -PSO_DIMM_TYPE EQU 6 ; < Dimm Type -PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map -PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket -PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed -PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel -PSO_MEM_TECH EQU 11 ; < Channel Memory Type -PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay -PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed -PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs -; ********************************** -; * CONDITIONAL PSO SPECIFIC ENTRIES -; ********************************** -; Condition Types -CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types -PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block -PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected -PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel -PSO_CONDITION_REG EQU 103 ; Reserved -PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types -; Action Types -PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types -PSO_ACTION_ODT EQU 120 ; < ODT values to override -PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override -PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override -PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override -PSO_ACTION_REG EQU 124 ; Reserved -PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration -PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types -CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types -; ***************************************************************************************** -; * -; * CONDITIONAL OVERRIDE TABLE MACROS -; * -; ***************************************************************************************** -MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ - DB PSO_MEMCLK_DIS - DB 10 - DB SocketID - DB ChannelID - DB Bit0Map - DB Bit1Map - DB Bit2Map - DB Bit3Map - DB Bit4Map - DB Bit5Map - DB Bit6Map - DB Bit7Map -ENDM - -CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ - DB PSO_CKE_TRI - DB 4 - DB SocketID - DB ChannelID - DB Bit0Map - DB Bit1Map -ENDM - -ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ - DB PSO_ODT_TRI - DB 6 - DB SocketID - DB ChannelID - DB Bit0Map - DB Bit1Map - DB Bit2Map - DB Bit3Map -ENDM - -CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ - DB PSO_CS_TRI - DB 10 - DB SocketID - DB ChannelID - DB Bit0Map - DB Bit1Map - DB Bit2Map - DB Bit3Map - DB Bit4Map - DB Bit5Map - DB Bit6Map - DB Bit7Map -ENDM - -NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ - DB PSO_MAX_DIMMS - DB 3 - DB SocketID - DB ChannelID - DB NumberOfDimmSlotsPerChannel -ENDM - -NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ - DB PSO_MAX_CHIPSELS - DB 3 - DB SocketID - DB ChannelID - DB NumberOfChipSelectsPerChannel -ENDM - -NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ - DB PSO_MAX_CHNLS - DB 3 - DB SocketID - DB ANY_CHANNEL - DB NumberOfChannelsPerSocket -ENDM - -OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ - PSO_BUS_SPEED - DB 10 - DB SocketID - DB ChannelID - DD TimingMode - DD BusSpeed -ENDM - -DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ - DB PSO_MEM_TECH - DB 6 - DB SocketID - DB ANY_CHANNEL - DD MemTechType -ENDM - -WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \ -Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ - DB PSO_WL_SEED - DB 11 - DB SocketID - DB ChannelID - DB Byte0Seed - DB Byte1Seed - DB Byte2Seed - DB Byte3Seed - DB Byte4Seed - DB Byte5Seed - DB Byte6Seed - DB Byte7Seed - DB ByteEccSeed -ENDM - -HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \ -Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ - DB PSO_RXEN_SEED - DB 20 - DB SocketID - DB ChannelID - DW Byte0Seed - DW Byte1Seed - DW Byte2Seed - DW Byte3Seed - DW Byte4Seed - DW Byte5Seed - DW Byte6Seed - DW Byte7Seed - DW ByteEccSeed -ENDM - -NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ - DB PSO_NO_LRDIMM_CS67_ROUTING - DB 3 - DB SocketID - DB ChannelID - DB 1 -ENDM - - -; ***************************************************************************************** -; * -; * CONDITIONAL OVERRIDE TABLE MACROS -; * -; ***************************************************************************************** -CONDITION_AND MACRO - DB PSO_CONDITION_AND - DB 0 -ENDM - -COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ - DB PSO_CONDITION_LOC - DB 3 - DB SocketMsk - DB ChannelMsk - DB DimmMsk -ENDM - -COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ - DB PSO_CONDITION_SPD - DB 3 - DB Byte - DB Mask - DB Value -ENDM - -COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ - DB PSO_CONDITION_REG - DB 11 - DB Access - DW Offset - DD Mask - DD Value -ENDM - -ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ - DB PSO_ACTION_ODT - DB 9 - DD Frequency - DB Dimms - DB QrDimms - DB DramOdt - DB QrDramOdt - DB DramDynOdt -ENDM - -ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ - DB PSO_ACTION_ADDRTMG - DB 10 - DD Frequency - DW DimmConfig - DD AddrTmg -ENDM - -ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ - DB PSO_ACTION_ODCCONTROL - DB 10 - DD Frequency - DW DimmConfig - DD OdcCtrl -ENDM - -ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ - DB PSO_ACTION_SLEWRATE - DB 10 - DD Frequency - DW DimmConfig - DD SlewRate -ENDM - -ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ - DB PSO_ACTION_SPEEDLIMIT - DB 9 - DW DimmConfig - DB Dimms - DW SpeedLimit15 - DW SpeedLimit135 - DW SpeedLimit125 -ENDM - -; ***************************************************************************************** -; * -; * END OF CONDITIONAL OVERRIDE TABLE MACROS -; * -; ***************************************************************************************** diff --git a/src/vendorcode/amd/agesa/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/Legacy/Proc/Dispatcher.c deleted file mode 100644 index fed63ed525..0000000000 --- a/src/vendorcode/amd/agesa/Legacy/Proc/Dispatcher.c +++ /dev/null @@ -1,161 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD binary block interface - * - * Contains the block entry function dispatcher - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Legacy - * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Dispatcher.h" -#include "Options.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CONST DISPATCH_TABLE DispatchTable[]; -extern AMD_MODULE_HEADER mCpuModuleID; - -/*---------------------------------------------------------------------------------------*/ -/** - * The Dispatcher is the entry point into the AGESA software. It takes a function - * number as entry parameter in order to invoke the published function - * - * @param[in,out] ConfigPtr - * - * @return AGESA Status. - * - */ -AGESA_STATUS -CALLCONV -AmdAgesaDispatcher ( - IN OUT VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - IMAGE_ENTRY ImageEntry; - MODULE_ENTRY ModuleEntry; - DISPATCH_TABLE *Entry; - UINT32 ImageStart; - UINT32 ImageEnd; - AMD_IMAGE_HEADER* AltImagePtr; - - Status = AGESA_UNSUPPORTED; - ImageEntry = NULL; - ModuleEntry = NULL; - ImageStart = 0xFFF00000; - ImageEnd = 0xFFFFFFFF; - AltImagePtr = NULL; - - Entry = (DISPATCH_TABLE *) DispatchTable; - while (Entry->FunctionId != 0) { - if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) { - Status = Entry->EntryPoint (ConfigPtr); - break; - } - Entry++; - } - - // 2. Try next dispatcher if possible, and we have not already got status back - if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) { - ModuleEntry = (MODULE_ENTRY) (UINT64) mCpuModuleID.NextBlock->ModuleDispatcher; - if (ModuleEntry != NULL) { - Status = (*ModuleEntry) (ConfigPtr); - } - } - - // 3. If not this image specific function, see if we can find alternative image instead - if (Status == AGESA_UNSUPPORTED) { - if ((((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0xFFFFFFFF ) || (((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0)) { - ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr; - ImageEnd = ImageStart + 4; - // Locate/test image base that matches this component - AltImagePtr = LibAmdLocateImage ((VOID *) (UINT64)ImageStart, (VOID *) (UINT64)ImageEnd, 4096, AGESA_ID); - if (AltImagePtr != NULL) { - //Invoke alternative Image - ImageEntry = (IMAGE_ENTRY) ((UINT64) AltImagePtr + AltImagePtr->EntryPointAddress); - Status = (*ImageEntry) (ConfigPtr); - } - } - } - - return (Status); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * The host environment interface of callout. - * - * @param[in] Func - * @param[in] Data - * @param[in,out] ConfigPtr - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -CALLCONV -AmdAgesaCallout ( - IN UINT32 Func, - IN UINT32 Data, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 Result; - Result = AGESA_UNSUPPORTED; - if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) { - return Result; - } - - Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr); - return (Result); -} diff --git a/src/vendorcode/amd/agesa/Legacy/Proc/Legacy.bat b/src/vendorcode/amd/agesa/Legacy/Proc/Legacy.bat deleted file mode 100644 index 0b79a987c1..0000000000 --- a/src/vendorcode/amd/agesa/Legacy/Proc/Legacy.bat +++ /dev/null @@ -1,286 +0,0 @@ -@echo off -echo ***************************************************************************** -echo * -echo * Copyright (c) 2011, Advanced Micro Devices, Inc. -echo * All rights reserved. -echo * -echo * Redistribution and use in source and binary forms, with or without -echo * modification, are permitted provided that the following conditions are met: -echo * * Redistributions of source code must retain the above copyright -echo * notice, this list of conditions and the following disclaimer. -echo * * Redistributions in binary form must reproduce the above copyright -echo * notice, this list of conditions and the following disclaimer in the -echo * documentation and/or other materials provided with the distribution. -echo * * Neither the name of Advanced Micro Devices, Inc. nor the names of -echo * its contributors may be used to endorse or promote products derived -echo * from this software without specific prior written permission. -echo * -echo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -echo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -echo * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -echo * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -echo * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -echo * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -echo * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -echo * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -echo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -echo * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -echo * -echo * *************************************************************************** - - -goto Begin -:Documentation -echo off -echo ************************************************************************** -echo * Legacy.Bat -echo * This batchfile establishes the build environment for an AGESA(TM) -echo * legacy build. -echo * -echo * Syntax: -echo * Legacy.bat Solution [DevTipPath] [DevKey] [DoxKey] [Release^|Debug] [Internal] -echo * Parameters: -echo * %% 1 Solution name. This is the AMD Platform Solution name that -echo * identifies the delivery package. No default, this -echo * parameter MUST be specified. This parameter MUST -echo * be specified before the DevTip Path parameter. -echo * %% 2 Path to the platform specific build directory. This is -echo * where the options file %%Solution%%Options.c is located, -echo * which contains the platform specific build option settings. -echo * If left blank, the default %%Solution%%Options.c file from -echo * the AGESA\Addendum directory is used. -echo * %% 3 Developer's key - open an interactive MSVS window. This parameter is -echo * optional, but when used it requires the first two parameters. -echo * %% 4 Documentation Key - requests a compilation of the DOxygen -echo * documentation files. key is "DOX". This parameter is -echo * optional, but when used it requires the first two parameters. -echo * %% 5 Build Configuration. There are two choices, "Release" and "Debug". -echo * Debug is the default choice if not specified. This parameter is -echo * optional, but when used it requires the first two parameters. -echo * %% 6 Internal solution file select - choose a internal solution file.This parameter -echo * is optional, but when used it requires the first two parameters. -echo * NOTE: The paths MUST have a trailing '\' character. -echo * -echo * The AGESA build environment requires the following environment -echo * variables MUST be defined for proper operation: -echo * $(AGESA_ROOT) - identifies the directory where the AGESA code -echo * is located. The top most dir; where AGESA.h is located. -echo * This must be the full path, eg D:\myPlatform\AGESA\ -echo * **** This var is expected to be set by the caller **** -echo * -echo * $(Solution) - identifies the Platform Solution being targeted -echo * $(AGESA_OptsDir) - identifies the directory where the platform -echo * options and customization files are located. -echo * This must be the full path -echo * -echo * Optional build environment variables -echo * -echo * set AGESA_B1_ADDRESS=0xFFF????? -echo * Sets the B1 image base address in the ROM (otherwise 0xFFFD0000). -echo * set AGESA_B2_ADDRESS=0xFFF????? -echo * Sets the B2 image base address in the ROM (otherwise 0xFFFA0000). -echo * -echo * NOTE: The paths MUST have a trailing '\' character. -echo ************************************************************************** -goto Exit - -:Begin -rem Clear working vars... -set DevKey= -set DoxKey= -set Solution= -set Configuration= - -rem set default to external file prefix none -set SolutionType= - -rem Validate the AGESA_ROOT variable -IF "%AGESA_ROOT%"=="" goto Else001 - rem User has set a path for Agesa_Root, verify that path... - IF EXIST %AGESA_ROOT%Agesa.h goto EndIf002 - rem Try adding trailing '\' - set AGESA_ROOT=%AGESA_ROOT%\ - IF EXIST %AGESA_ROOT%Agesa.h goto EndIf003 - echo Build ERROR: Environment variable AGESA_ROOT is invalid, - echo Build ERROR: Could not find file Agesa.h at: %AGESA_ROOT% - pause - goto Documentation - :EndIf003 - :EndIf002 - goto EndIf001 -:Else001 - echo Build ERROR: Required environment variable missing: AGESA_ROOT - pause - goto Documentation -:EndIf001 - -rem Start processing the input parameters... -:DoLoop - rem Switch (%1) - IF /I "%1"=="DevKey" goto Case001 - IF /I "%1"=="Maranello" goto Case002 - IF /I "%1"=="DevTest" goto Case002 - IF /I "%1"=="Danube" goto Case002 - IF /I "%1"=="DanNi" goto Case002 - IF /I "%1"=="Nile" goto Case002 - IF /I "%1"=="Dragon" goto Case002 - IF /I "%1"=="SanMarino" goto Case002 - IF /I "%1"=="Scorpius" goto Case002 - IF /I "%1"=="Sabine" goto Case002 - IF /I "%1"=="Lynx" goto Case002 - IF /I "%1"=="Brazos" goto Case002 - IF /I "%1"=="DOX" goto Case009 - IF /I "%1"=="Debug" goto Case011 - IF /I "%1"=="Release" goto Case011 - IF /I "%1"=="Internal" goto Case012 - IF "%1"=="" goto Case006 - goto Case004 - :Case001 - rem Case 1: Special command param - set DevKey=DevKey - goto EndSwitch - :Case002 - rem Case 2: Solution name parameter - rem Set the Platform Solution name for the build environment - rem Validation of the names was done by the IF's at the top of DoLoop - set Solution=%1 - goto EndSwitch - :Case004 - rem Case 4: Path param, check for validity - rem Check if parameter matches the default - rem Check for shortcut versions of the default. Also - rem checking for missing trailing '\' - IF /I "%1"=="Addendum" goto Then040 - IF /I "%1"=="Addendum\" goto Then040 - IF /I "%1"=="..\Addendum" goto Then040 - IF /I "%1"=="..\Addendum\" goto Then040 - IF /I "%1"=="..\..\Addendum" goto Then040 - IF /I "%1"=="..\..\Addendum\" goto Then040 - goto Else040 - :Then040 - set AGESA_OptsDir=%AGESA_ROOT%Addendum\ - Echo Build WARNING: User selected the default options path. - goto EndIf040 - :Else040 - set AGESA_OptsDir=%1 - rem Non-default path given, - rem Validate the AGESA_OptsDir parameter ( %%1 = %1 )... - IF /I "%Solution%"=="" goto Else042 - IF EXIST %AGESA_OptsDir%%Solution%Options.c goto EndIf044 - rem Check if param was missing trailing '\'... - set AGESA_OptsDir=%AGESA_OptsDir%\ - IF EXIST %AGESA_OptsDir%%Solution%Options.c goto EndIf045 - rem If using the default, assume the release file is in place. - rem Could not find options file, post an error - Echo Build ERROR: Path to AGESA options file is not valid... - Echo . . Could not find options file: %AGESA_OptsDir%%Solution%Options.c - set AGESA_OptsDir= - set Solution= - exit /B 5 - :EndIf045 - :EndIf044 - goto EndIf042 - :Else042 - rem Else042 - parameter ordering error, need to specify solution before tip path - Echo Build ERROR: The 'Solution' name was not recognized or - Echo The Solution must be specified before the Development tip path - Echo . . . Legacy.bat Solution [DevTipPath] [DevKey] [DoxKey] - exit /B 4 - :EndIf042 - :EndIf040 - goto EndSwitch - :Case006 - rem Case 6: Parameter is blank, end of list - rem Validate the required Environment Variables - IF /I "%Solution%"=="" goto Else066 - IF NOT "%AGESA_OptsDir%"=="" goto Else060 - Rem No path param specified. Use the default file shipped with the AGESA package... - Echo Build WARNING: Using default options file. - set AGESA_OptsDir=%AGESA_ROOT%Addendum\ - goto EndIf060 - :Else060 - rem Else060 - tip path may have been set by caller prior to call, - rem Validate the AGESA_OptsDir parameter ( %%AGESA_OptsDir = %AGESA_OptsDir% )... - IF EXIST %AGESA_OptsDir%%Solution%Options.c goto EndIf061 - rem Check if param was missing trailing '\'... - set AGESA_OptsDir=%AGESA_OptsDir%\ - IF EXIST %AGESA_OptsDir%%Solution%Options.c goto EndIf062 - rem If using the default, assume the release file is in place. - rem Could not find options file, post an error - Echo Build ERROR: Path to AGESA options file is not valid... - Echo . . Could not find options file: %AGESA_OptsDir%%Solution%Options.c - set AGESA_OptsDir= - set Solution= - exit /B 4 - :EndIf062 - :EndIf061 - :EndIf060 - goto EndIf066 - :Else066 - rem Else066 - parameter missing error, need to specify 'solution' - Echo Build ERROR: The Platform Solution name must be specified: - Echo . . . Legacy.bat Solution [DevTipPath] [DevKey] [DoxKey] - exit /B 4 - :EndIf066 - goto EndDo - :Case009 - rem Case 9: Documentation generation key - set DoxKey=DoxKey - goto EndSwitch - :Case011 - rem Case 11: Build Configuration - set Configuration=%1 - goto EndSwitch - :Case012 - rem Case 12: Select Internal solution file prefix - set SolutionType=%1 - goto EndSwitch - :EndSwitch - SHIFT - goto DoLoop -:EndDo - -rem # Ensure that Microsoft Visual Studio 2005 is installed on this machine. -IF NOT "%VS80COMNTOOLS%"=="" goto EndIf95 -echo --------------------------------------------------------------------- -echo - Building AGESA ARCH2008 requires Microsoft Visual Studio 2005 - -echo - Install Visual Studio 2005 and confirm environment - -echo - variable VS80COMNTOOLS is present. - -echo --------------------------------------------------------------------- -pause -exit -:EndIf95 - -rem set the Visual Studio 32-bit development environment -call "%VS80COMNTOOLS%vsvars32.bat" - -rem Launch the documentation generator if selected by the user -IF NOT "%DoxKey%"=="DoxKey" goto EndIf100 - devenv %AGESA_ROOT%Proc\AgesaDoc.sln /Rebuild "Release|Win32" -:EndIf100 - -rem Use the default build configuration if none was specified. -IF NOT "%Configuration%"=="" goto EndIf110 - set Configuration=Debug -:EndIf110 - -rem Check image bases -IF NOT "%AGESA_B1_ADDRESS%"=="" goto EndIf120 - set AGESA_B1_ADDRESS=0xFFFD0000 -:EndIf120 -IF NOT "%AGESA_B2_ADDRESS%"=="" goto EndIf130 - set AGESA_B2_ADDRESS=0xFFFA0000 -:EndIf130 - -rem Check if the 'secret' developers' key was used, open an interactive VS window -IF NOT "%DevKey%"=="DevKey" goto Else140 - set DevKey= - rem This is the command to open an interactive development window ... - start /NORMAL devenv.exe %AGESA_ROOT%Legacy\Proc\%Solution%%SolutionType%Legacy.sln /ProjectConfig "%Configuration%|Win32" - goto EndIf140 -:Else140 - rem Else140 - This is the command to perform a background or automated build ... - devenv %AGESA_ROOT%Legacy\Proc\%Solution%%SolutionType%Legacy.sln /Rebuild "%Configuration%|Win32" -:EndIf140 -:Exit -exit /B 0 diff --git a/src/vendorcode/amd/agesa/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/Legacy/Proc/agesaCallouts.c deleted file mode 100644 index ffb712ef0b..0000000000 --- a/src/vendorcode/amd/agesa/Legacy/Proc/agesaCallouts.c +++ /dev/null @@ -1,397 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU AGESA Callout Functions - * - * Contains code to set / get useful platform information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Dispatcher.h" -#include "cpuServices.h" -#include "Ids.h" -#include "Filecode.h" - -#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - (AGESA ONLY) - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Call the host environment interface to do the warm or cold reset. - * - * @param[in] ResetType Warm or Cold Reset is requested - * @param[in,out] StdHeader Config header - * - */ -VOID -AgesaDoReset ( - IN UINTN ResetType, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - WARM_RESET_REQUEST Request; - - // Clear warm request bit and set state bits to the current post stage - GetWarmResetFlag (StdHeader, &Request); - Request.RequestBit = FALSE; - Request.StateBits = Request.PostStage; - SetWarmResetFlag (StdHeader, &Request); - - Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Call the host environment interface to allocate buffer in main system memory. - * - * @param[in] FcnData - * @param[in,out] AllocParams Heap manager parameters - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaAllocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *AllocParams - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to deallocate buffer in main system memory. - * - * @param[in] FcnData - * @param[in,out] DeallocParams Heap Manager parameters - * - * @return The AGESA Status returned from the callout. - */ -AGESA_STATUS -AgesaDeallocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *DeallocParams - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Call the host environment interface to Locate buffer Pointer in main system memory - * - * @param[in] FcnData - * @param[in,out] LocateParams Heap manager parameters - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaLocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *LocateParams - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to launch APs - * - * @param[in] ApicIdOfCore - * @param[in,out] LaunchApParams - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaRunFcnOnAp ( - IN UINTN ApicIdOfCore, - IN AP_EXE_PARAMS *LaunchApParams - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to read an SPD's content. - * - * @param[in] FcnData - * @param[in,out] ReadSpd - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaReadSpd ( - IN UINTN FcnData, - IN OUT AGESA_READ_SPD_PARAMS *ReadSpd - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to read an SPD's content. - * - * @param[in] FcnData - * @param[in,out] ReadSpd - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaReadSpdRecovery ( - IN UINTN FcnData, - IN OUT AGESA_READ_SPD_PARAMS *ReadSpd - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] FcnData - * @param[in,out] MemData - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaHookBeforeDramInitRecovery ( - IN UINTN FcnData, - IN OUT MEM_DATA_STRUCT *MemData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, (UINT32)FcnData, MemData); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] FcnData - * @param[in,out] MemData - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaHookBeforeDramInit ( - IN UINTN FcnData, - IN OUT MEM_DATA_STRUCT *MemData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)FcnData, MemData); - - return Status; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] FcnData - * @param[in,out] MemData - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaHookBeforeDQSTraining ( - IN UINTN FcnData, - IN OUT MEM_DATA_STRUCT *MemData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)FcnData, MemData); - - return Status; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] FcnData - * @param[in,out] MemData - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaHookBeforeExitSelfRefresh ( - IN UINTN FcnData, - IN OUT MEM_DATA_STRUCT *MemData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData); - - return Status; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] Data - * @param[in,out] IdsCalloutData - * - * @return The AGESA Status returned from the callout. - * - */ - - -AGESA_STATUS -AgesaGetIdsData ( - IN UINTN Data, - IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData); - - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIE slot reset control - * - * - * - * @param[in] FcnData Function data - * @param[in] ResetInfo Reset information - * @retval Status Agesa status - */ - -AGESA_STATUS -AgesaPcieSlotResetControl ( - IN UINTN FcnData, - IN PCIe_SLOT_RESET_INFO *ResetInfo - ) -{ - AGESA_STATUS Status; - Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo); - return Status; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/Legacy/Proc/arch2008.asm deleted file mode 100644 index d30790621c..0000000000 --- a/src/vendorcode/amd/agesa/Legacy/Proc/arch2008.asm +++ /dev/null @@ -1,2674 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; Workfile: arch2008.asm $Revision: 37157 $ $Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $ -; -; Description: ARCH2008.ASM - AGESA Architecture 2008 Wrapper Template -; -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** - - .XLIST - INCLUDE agesa.inc - INCLUDE acwrapg.inc ; Necessary support file as part of wrapper, including but not limited to segment start/end macros. - INCLUDE acwrap.inc ; IBVs may specify host BIOS-specific include files required when building. - INCLUDE cpcarmac.inc - INCLUDE bridge32.inc - .LIST - .586p - .mmx - - -;---------------------------------------------------------------------------- -; Local definitions -;---------------------------------------------------------------------------- - -sOemCallout STRUCT - FuncName DD ? ; Call out function name - FuncPtr DW ? ; Call out function pointer -sOemCallout ENDS - -sOemEventHandler STRUCT - ClassCode DD ? ; AGESA event log sub-class code - FuncPtr DW ? ; Event handler function pointer -sOemEventHandler ENDS - -;; A typical legacy BIOS implementation may require the E000 and F000 segments -;; to be cached. -EXE_CACHE_REGION_BASE_0 EQU 0E0000h -EXE_CACHE_REGION_SIZE_0 EQU 20000h - -;; In this sample implementation, the B1 and B2 images are placed next to each -;; other in the BIOS ROM to help with the maximization of cached code. -EXE_CACHE_REGION_BASE_1 EQU AGESA_B1_ADDRESS -EXE_CACHE_REGION_SIZE_1 EQU 40000h - -;; The third region is not needed in our example. -EXE_CACHE_REGION_BASE_2 EQU 0 -EXE_CACHE_REGION_SIZE_2 EQU 0 - - -;---------------------------------------------------------------------------- -; PERSISTENT SEGMENT -; This segment is required to be present throughout all BIOS execution. -;---------------------------------------------------------------------------- - -AMD_PERSISTENT_START - - -;---------------------------------------------------------------------------- -; Instantiate the global descriptor table -;---------------------------------------------------------------------------- - -AMD_BRIDGE_32_GDT AMD_GDT ; Instantiate the global descriptor table - ; required by the push-high mechanism. - - -;---------------------------------------------------------------------------- -; Declare the external routines required in the persistent segment -;---------------------------------------------------------------------------- - -;+------------------------------------------------------------------------- -; -; AmdDfltRet -; -; Entry: -; None -; -; Exit: -; None -; -; Modified: -; None -; -; Purpose: -; Near stub procedure. Simply perform a retn instruction. -; -EXTERN AmdDfltRet:NEAR - - -;+------------------------------------------------------------------------- -; -; AmdDfltRetFar -; -; Entry: -; None -; -; Exit: -; None -; -; Modified: -; None -; -; Purpose: -; Far stub procedure. Simply perform a retf instruction. -; -EXTERN AmdDfltRetFar:FAR - - -;---------------------------------------------------------------------------- -; Declare the optional external routines in the persistent segment -;---------------------------------------------------------------------------- - -;+--------------------------------------------------------------------------- -; -; myModuleTypeMismatchHandler (Example) -; -; Entry: -; ESI - Pointer to the EVENT_PARAMS structure of the failure. -; [ESI].DataParam1 - Socket -; [ESI].DataParam2 - DCT -; [ESI].DataParam3 - Channel -; [ESI].DataParam4 - 0x00000000 -; -; Exit: -; None -; -; Modified: -; None -; -; Purpose: -; This procedure can be used to react to a memory module type -; mismatch error discovered by the AGESA code. Actions taken -; may include, but are not limited to: -; Logging the event to NV for display later -; Reset, excluding the mismatch on subsequent reboot -; Do nothing -; -; Dependencies: -; None -; -EXTERN myModuleTypeMismatchHandler(AmdDfltRet):NEAR - -;+--------------------------------------------------------------------------- -; -; oemPlatformConfigInit (Optional) -; -; Entry: -; EDI - 32-bit flat pointer to the PLATFORM_CONFIGURATION to be -; passed in to the next AGESA entry point. -; -; typedef struct { -; IN PERFORMANCE_PROFILE PlatformProfile; -; IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; -; IN UINT8 CoreLevelingMode; -; IN PLATFORM_C1E_MODES C1eMode; -; IN UINT32 C1ePlatformData; -; IN UINT32 C1ePlatformData1; -; IN UINT32 C1ePlatformData2; -; IN BOOLEAN UserOptionDmi; -; IN BOOLEAN UserOptionPState; -; IN BOOLEAN UserOptionSrat; -; IN BOOLEAN UserOptionSlit; -; IN BOOLEAN UserOptionWhea; -; IN UINT32 PowerCeiling; -; IN BOOLEAN PstateIndependent; -; } PLATFORM_CONFIGURATION; -; -; typedef struct { -; IN UINT8 Socket; -; IN UINT8 Link; -; IN UINT8 LoFreq; -; IN UINT8 HighFreq; -; IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis; -; IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis; -; } CPU_HT_DEEMPHASIS_LEVEL; -; -; typedef struct { -; IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode; -; IN BOOLEAN UseHtAssist; -; IN BOOLEAN UseAtmMode; -; IN BOOLEAN Use32ByteRefresh; -; IN BOOLEAN UseVariableMctIsocPriority; -; } PERFORMANCE_PROFILE; -; -; Exit: -; None -; -; Modified: -; None -; -; Purpose: -; Provide a single hook routine to modify the parameters of a -; PLATFORM_CONFIGURATION structure before any entry point that -; has such a structure as an input. -; -; Dependencies: -; None -; -; Example: -; If your platform is running in UMA mode, the following code -; may be added: -; mov (PLATFORM_CONFIGURATION PTR [edi]).PlatformProfile.PlatformControlFlowMode, UmaDr -; -EXTERN oemPlatformConfigInit(AmdDfltRetFar):FAR - -;+--------------------------------------------------------------------------- -; -; oemCallout (Optional) -; -; Entry: -; ECX - Callout function number -; EDX - Function-specific UINTN -; ESI - Pointer to function specific data -; -; Exit: -; EAX - Contains the AGESA_STATUS return code. -; -; Modified: -; None -; -; Purpose: -; The default call out router function which resides in the same -; segment as the push-high bridge code. -; -; Dependencies: -; None -; -EXTERN oemCallout(AmdDfltRet):NEAR - - -;---------------------------------------------------------------------------- -; Define the sample wrapper routines for the persistent segment -;---------------------------------------------------------------------------- - -;+--------------------------------------------------------------------------- -; -; AmdBridge32 -; -; Entry: -; EDX - A Real Mode FAR pointer using seg16:Offset16 format that -; points to a local host environment call-out router. If -; this pointer is not equal to zero, then this pointer is -; used as the call-out router instead of the standard -; OemCallout. This may be useful when the call-out router -; is not located in the same segment as the AmdBridge32 and -; AmdCallout16 routines. -; ESI - A Flat Mode pointer (32-bit address) that points to the -; configuration block (AMD_CONFIG_PARAMS) for the AGESA -; software function. -; -; Exit: -; EAX - Contains the AGESA_STATUS return code. -; -; Modified: -; None -; -; Purpose: -; Execute an AGESA software function through the Push-High interface. -; -; Dependencies: -; This procedure requires a stack. The host environment must use the -; provided service function to establish the stack environment prior -; to making the call to this procedure. -; -AmdBridge32 PROC FAR PUBLIC - AMD_BRIDGE_32 AMD_GDT ; use the macro for the body - ret -AmdBridge32 ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdEnableStack -; -; Entry: -; BX - Return address -; -; Exit: -; EAX - Contains the AGESA_STATUS return code. -; SS:ESP - Points to the private stack location for this processor core. -; ECX - Upon success, contains this processor core's stack size in bytes. -; -; Modified: -; EAX, ECX, EDX, EDI, ESI, ESP, DS, ES -; -; Purpose: -; This procedure is used to establish the stack within the host environment. -; -; Dependencies: -; The host environment must use this procedure and not rely on any other -; sources to create the stack region. -; -AmdEnableStack PROC NEAR PUBLIC - AMD_ENABLE_STACK - ;; EAX = AGESA_SUCCESS, The stack space has been allocated for this core. - ;; EAX = AGESA_WARNING, The stack has already been set up. SS:ESP is set - ;; to stack top, and ECX is the stack size in bytes. - jmp bx -AmdEnableStack ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdDisableStack -; -; Entry: -; BX - Return address -; -; Exit: -; EAX - Contains the AGESA_STATUS return code. -; -; Modified: -; EAX, ECX, EDX, ESI, ESP -; -; Purpose: -; This procedure is used to remove the pre-memory stack from within the -; host environment. -; The exit state for the BSP is described as follows: -; Memory region 00000-9FFFF MTRRS are set as WB memory. -; Processor Cache is enabled (CD bit is cleared). -; MTRRs used for execution cache are kept. -; Cache content is flushed (invalidated without write-back). -; Any family-specific clean-up done. -; The exit state for the APs is described as follows: -; Memory region 00000-9FFFF MTRRS are set as WB memory. -; Memory region A0000-DFFFF MTRRS are set as UC IO. -; Memory region E0000-FFFFF MTRRS are set as UC memory. -; MTRRs used for execution cache are cleared. -; Processor Cache is disabled (CD bit is set). -; Top-of-Memory (TOM) set to the system top of memory as determined -; by the memory initialization routines. -; System lock command is enabled. -; Any family-specific clean-up done. -; -; Dependencies: -; The host environment must use this procedure and not rely on any other -; sources to break down the stack region. -; If executing in 16-bit code, the host environment must establish the -; "Big Real" mode of 32-bit addressing of data. -; -AmdDisableStack PROC NEAR PUBLIC - AMD_DISABLE_STACK - ;; EAX = AGESA_SUCCESS, The stack space has been disabled for this core. - jmp bx -AmdDisableStack ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdCallout16 -; -; Entry: -; [esp+8] - Func -; [esp+12] - Data -; [esp+16] - Configuration Block -; [esp+4] - Return address to AGESA -; -; Exit: -; EAX - Contains the AGESA_STATUS return code. -; -; Modified: -; None -; -; Purpose: -; Execute callback from the push-high interface. -; -; Dependencies: -; None -; -AmdCallout16 PROC FAR PUBLIC ; declare the procedure - AMD_CALLOUT_16 oemCallout ; use the macro for the body - ret -AmdCallout16 ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdProcessAgesaErrors (Optional) -; -; Entry: -; AL - Heap status of the AGESA entry point that was just invoked. -; EBX - AGESA image base address. -; EDX - Segment / Offset of the appropriate callout router function. -; -; Exit: -; None -; -; Modified: -; None -; -; Purpose: -; This procedure is used to handle any errors that may have occurred -; during an AGESA entry point. -; -; Dependencies: -; None -; -AmdProcessAgesaErrors PROC FAR PUBLIC - LOCAL localCpuInterfaceBlock:EVENT_PARAMS - - pushad - xor edi, edi - mov di, ss - shl edi, 4 - lea esi, localCpuInterfaceBlock - add esi, edi - - ; Fill default config block - mov (EVENT_PARAMS PTR [esi]).StdHeader.Func, AMD_READ_EVENT_LOG - mov (EVENT_PARAMS PTR [esi]).StdHeader.ImageBasePtr, ebx - mov (EVENT_PARAMS PTR [esi]).StdHeader.AltImageBasePtr, 0 - mov (EVENT_PARAMS PTR [esi]).StdHeader.HeapStatus, al - mov edi, SEG AmdCallout16 - shl edi, 4 - add edi, OFFSET AmdCallout16 - mov (EVENT_PARAMS PTR [esi]).StdHeader.CalloutPtr, edi - - ; Flush the event log searching for, and handling all monitored events - xor eax, eax - .while (eax == 0) - push edx - call AmdBridge32 - pop edx - .if (eax == AGESA_SUCCESS) - mov eax, (EVENT_PARAMS PTR [esi]).EventInfo - .if (eax != 0) - lea di, cs:AgesaEventTable - -loopThruTable: - cmp di, OFFSET cs:AgesaEventTableEnd - jae unhandledEvent - - cmp eax, cs:[di].sOemEventHandler.ClassCode - je FoundMatch - add di, SIZEOF sOemEventHandler - jmp loopThruTable - -FoundMatch: - mov bx, cs:[di].sOemEventHandler.FuncPtr - call bx - -unhandledEvent: - xor eax, eax - .else - mov al, 1 - .endif - .endif - .endw - popad - ret - -AmdProcessAgesaErrors ENDP - - -;---------------------------------------------------------------------------- -; Define the error handler table -;---------------------------------------------------------------------------- - -AgesaEventTable LABEL BYTE - ;; Add entries as desired - ;;--------- - ;; EXAMPLE - ;;--------- - sOemEventHandler <MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, OFFSET myModuleTypeMismatchHandler> -AgesaEventTableEnd LABEL BYTE - - -AMD_PERSISTENT_END - - - - -;---------------------------------------------------------------------------- -; RECOVERY SEGMENT -; This segment resides in the classic 'boot-block,' and is used -; for recovery. -;---------------------------------------------------------------------------- - -AMD_RECOVERY_START - - -;---------------------------------------------------------------------------- -; Declare the external routines required in the recovery segment -;---------------------------------------------------------------------------- - -;+--------------------------------------------------------------------------- -; -; myReadSPDRecovery (Required for proper recovery mode operation) -; -; Entry: -; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure. -; -; typedef struct { -; IN OUT AMD_CONFIG_PARAMS StdHeader; -; IN UINT8 SocketId; -; IN UINT8 MemChannelId; -; IN UINT8 DimmId; -; IN OUT UINT8 *Buffer; -; IN OUT MEM_DATA_STRUCT *MemData; -; } AGESA_READ_SPD_PARAMS; -; -; Exit: -; EAX - Contains the AGESA_STATUS return code. -; AGESA_SUCCESS Indicates the SPD block for the indicated -; DIMM was read successfully. -; AGESA_BOUNDS_CHK The specified DIMM is not present. -; AGESA_UNSUPPORTED This is a required function, so this -; value being returned causes a critical -; error response value from the AGESA -; software function and no memory initialized. -; AGESA_ERROR The DIMM SPD read process has generated -; communication errors. -; -; Modified: -; None -; -; Purpose: -; This call out reads a block of memory SPD data and places it -; into the provided buffer. -; -; Dependencies: -; None -; -EXTERN myReadSPDRecovery:NEAR - - -;---------------------------------------------------------------------------- -; Define the sample wrapper routines for the recovery segment -;---------------------------------------------------------------------------- - -;+--------------------------------------------------------------------------- -; -; AmdInitResetWrapper -; -; Entry: -; DS - 0000 with 4 gigabyte access -; ES - 0000 with 4 gigabyte access -; -; Exit: -; None -; -; Modified: -; None -; -; Purpose: -; A minimal initialization of the processor core is performed. This -; procedure must be called by all processor cores. The code path -; separates the BSP from the APs and performs a separate and appropriate -; list of tasks for each class of core. -; For the BSP, the following actions are performed: -; Internal heap sub-system initialization -; Primary non-coherent HyperTransportT link initialization -; Return to the host environment to test for Recovery Mode. -; The AP processor cores do not participate in the recovery process. -; However, they execute this routine after being released to execute -; by the BSP during the main boot process. Their actions include the -; following: -; Internal heap sub-system initialization -; Proceed to a wait loop waiting for commands from the BSP -; -; For the cache regions, up to three regions of execution cache can be -; allocated following the following rules: -; 1. Once a region is allocated, it cannot be de-allocated. However, it -; can be expanded. -; 2. At most, two of the three regions can be located above 1 MByte. A -; region failing this rule is ignored. -; 3. All region addresses must be at or above the 0x000D0000 linear -; address. A region failing this rule is ignored. -; 4. The address is aligned on a 32-KByte boundary. Starting addresses -; is rounded down to the nearest 32-Kbyte boundary. -; 5. The execution cache size must be a multiple of 32 KByte. Size is -; rounded up to the next multiple of 32 KByte. -; 6. A region must not span either the 1-MByte boundary or the 4-GByte -; boundary. Allocated size is truncated to not span the boundary. -; 7. The granted cached execution regions, address, and size are calculated -; based on the available cache resources of the processor core. -; Allocations are made up to the limit of cache available on the -; installed processor. -; Warning: Enabling instruction cache outside of this interface can cause -; data corruption. -; -; Dependencies: -; This procedure is expected to be executed soon after a system reset -; for the main boot path or resume path of execution. -; -; This procedure requires a stack. -; -; Because the heap system is not yet operational at the point of the -; interface call, the host environment must allocate the storage for -; the AMD_RESET_PARAMS structure before making the first call to -; AmdCreateStruct. This is the ByHost method of allocation. -; -AmdInitResetWrapper PROC NEAR PUBLIC - local localCfgBlock:AMD_INTERFACE_PARAMS - local localResetParams:AMD_RESET_PARAMS - - pushad - - ; Prepare for the call to initialize the input parameters for AmdInitReset - xor eax, eax - mov ax, ss - shl eax, 4 - lea esi, localCfgBlock - add esi, eax - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 - mov edx, SEG AmdCallout16 - shl edx, 4 - add edx, OFFSET AmdCallout16 - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx - - ; Use the 'ByHost' allocation method because the heap has not been initialized as of yet. - mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESET - mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, ByHost - mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, sizeof AMD_RESET_PARAMS - lea edx, localResetParams - add edx, eax - push edx - mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr, edx - mov dx, SEG AmdCalloutRouterRecovery - shl edx, 16 - mov dx, OFFSET AmdCalloutRouterRecovery - push edx - call AmdBridge32 - pop edx - pop esi - - ; The structure has been initialized. Now modify the default settings as desired. - - ; Allocate the execution cache to maximize the amount of code in ROM that is cached. - ; Placing the B1 and B2 images near one another is a good way to ensure the AGESA code - ; is cached. - mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_0 - mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_0 - mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_1 - mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_1 - mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_2 - mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_2 - - ; Call in to the AmdInitReset entry point - push edx - call AmdBridge32 - pop edx - - ;; EAX = AGESA_STATUS - ;; AGESA_SUCCESS Early initialization completed successfully. - ;; AGESA_WARNING One or more of the execution cache allocation - ;; rules were violated, but an adjustment was made - ;; and space was allocated. - ;; AGESA_ERROR One or more of the execution cache allocation rules - ;; were violated, which resulted in a requested cache - ;; region to not be allocated. - ;; The storage space allocated for the AMD_RESET_PARAMS - ;; structure is insufficient. - - .if (eax != AGESA_SUCCESS) - mov al, (AMD_RESET_PARAMS ptr [esi]).StdHeader.HeapStatus - mov ebx, AGESA_B1_ADDRESS - call AmdProcessAgesaErrors - .endif - - - ;; Here are what the MTRRs should look like based off of the CacheRegions specified above: - - ;; Fixed-Range MTRRs - ;; Name Address Value - ;; ---------------- -------- ---------------- - ;; MTRRfix4k_E0000 0000026C 0505050505050505 - ;; MTRRfix4k_E8000 0000026D 0505050505050505 - ;; MTRRfix4k_F0000 0000026E 0505050505050505 - ;; MTRRfix4k_F8000 0000026F 0505050505050505 - ;; MTRRdefType 000002FF 0000000000000C00 - ;; - ;; Variable-Range MTRRs and IO Range - ;; MTRRphysBase(n) MTRRphysMask(n) - ;; ----------------- ----------------- - ;; n=0 0000000000000000 0000000000000000 - ;; n=1 0000000000000000 0000000000000000 - ;; n=2 0000000000000000 0000000000000000 - ;; n=3 0000000000000000 0000000000000000 - ;; n=4 0000000000000000 0000000000000000 - ;; n=5 Heap Base (Varies by core) 0000FFFFFFFF0800 - ;; n=6 AGESA_B1_ADDRESS | 6 0000FFFFFFFC0800 - ;; n=7 0000000000000000 0000000000000000 - - - ;; Because the allocation method is 'ByHost,' the call to AMD_RELEASE_STRUCT is - ;; not necessary. Stack space reclamation is left up to the host BIOS. - - popad - ret - - -AmdInitResetWrapper ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdInitRecoveryWrapper -; -; Entry: -; DS - 0000 with 4 gigabyte access -; ES - 0000 with 4 gigabyte access -; -; Exit: -; None -; -; Modified: -; None -; -; Purpose: -; Perform a minimum initialization of the processor and memory to -; support a recovery mode flash ROM update. -; For the BSP, the following actions are performed: -; Configuration of CPU core for recovery process -; Minimal initialization of some memory -; The AP processor cores do not participate in the recovery process. -; No actions or tasks are performed by the AP cores for this time point. -; -; Dependencies: -; This procedure requires a stack. The host environment must use one of -; the provided service functions to establish the stack environment prior -; to making the call to this procedure. -; -AmdInitRecoveryWrapper PROC NEAR PUBLIC - local localCfgBlock:AMD_INTERFACE_PARAMS - - pushad - - ; Prepare for the call to create and initialize the input parameters for AmdInitRecovery - xor eax, eax - mov ax, ss - shl eax, 4 - lea esi, localCfgBlock - add esi, eax - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 - mov edx, SEG AmdCallout16 - shl edx, 4 - add edx, OFFSET AmdCallout16 - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx - - mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RECOVERY - mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap - mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 - push esi - mov dx, SEG AmdCalloutRouterRecovery - shl edx, 16 - mov dx, OFFSET AmdCalloutRouterRecovery - push edx - call AmdBridge32 - pop edx - - mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr - - ; The structure has been initialized. Now modify the default settings as desired. - - - ; Call in to the AmdInitRecovery entry point - push edx - call AmdBridge32 - pop edx - - ;; EAX = AGESA_STATUS - ;; AGESA_SUCCESS The function has completed successfully. - ;; AGESA_WARNING One or more of the allocation rules were violated, - ;; but an adjustment was made and space was allocated. - ;; AGESA_ERROR One or more of the allocation rules were violated, - ;; which resulted in a requested cache region to not be - ;; allocated. - ;; AGESA_FATAL No memory was found in the system. - - .if (eax != AGESA_SUCCESS) - mov al, (AMD_RECOVERY_PARAMS ptr [esi]).StdHeader.HeapStatus - mov ebx, AGESA_B1_ADDRESS - call AmdProcessAgesaErrors - .endif - - ; Allow AGESA to free the space used by AmdInitRecovery - pop esi - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT - call AmdBridge32 - - popad - ret -AmdInitRecoveryWrapper ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdCalloutRouterRecovery -; -; Entry: -; ECX - Callout function number -; EDX - Function-specific UINTN -; ESI - Pointer to function specific data -; -; Exit: -; EAX - Contains the AGESA_STATUS return code. -; -; Modified: -; None -; -; Purpose: -; The call out router function for AmdInitReset and -; AmdInitRecovery. -; -; Dependencies: -; None -; -AmdCalloutRouterRecovery PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES - xor ax, ax - mov ds, ax - mov es, ax - lea di, cs:CalloutRouterTableRecovery - mov eax, AGESA_UNSUPPORTED - -loopThruTable: - cmp di, OFFSET cs:CalloutRouterTableRecoveryEnd - jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED - cmp ecx, cs:[di].sOemCallout.FuncName - je FoundMatch - add di, SIZEOF sOemCallout - jmp loopThruTable - -FoundMatch: - mov bx, cs:[di].sOemCallout.FuncPtr - call bx - -amdCpuCalloutExit: - ret -AmdCalloutRouterRecovery ENDP - - -;---------------------------------------------------------------------------- -; Define the callout dispatch table for the recovery segment -;---------------------------------------------------------------------------- - -CalloutRouterTableRecovery LABEL BYTE - ;; Standard B1 implementations only need the SPD reader call out function to be implemented. - sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDRecovery> -CalloutRouterTableRecoveryEnd LABEL BYTE - - -AMD_RECOVERY_END - - - -;---------------------------------------------------------------------------- -; PRE-MEMORY SEGMENT -; This segment must be uncompressed in the ROM image. -;---------------------------------------------------------------------------- - -AMD_PREMEM_START - - -;---------------------------------------------------------------------------- -; Declare the external routines required in the recovery segment -;---------------------------------------------------------------------------- - -;+--------------------------------------------------------------------------- -; -; myReadSPDPremem (Required) -; -; Entry: -; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure -; -; typedef struct { -; IN OUT AMD_CONFIG_PARAMS StdHeader; -; IN UINT8 SocketId; -; IN UINT8 MemChannelId; -; IN UINT8 DimmId; -; IN OUT UINT8 *Buffer; -; IN OUT MEM_DATA_STRUCT *MemData; -; } AGESA_READ_SPD_PARAMS; -; -; Exit: -; EAX - Contains the AGESA_STATUS return code. -; AGESA_SUCCESS Indicates the SPD block for the indicated -; DIMM was read successfully. -; AGESA_BOUNDS_CHK The specified DIMM is not present. -; AGESA_UNSUPPORTED This is a required function, so this -; value being returned causes a critical -; error response value from the AGESA -; software function and no memory initialized. -; AGESA_ERROR The DIMM SPD read process has generated -; communication errors. -; -; Modified: -; None -; -; Purpose: -; This call out reads a block of memory SPD data and places it -; into the provided buffer. -; -; Dependencies: -; None -; -EXTERN myReadSPDPremem:NEAR - -;+------------------------------------------------------------------------- -; -; AmdDfltRetPremem -; -; Entry: -; None -; -; Exit: -; None -; -; Modified: -; None -; -; Purpose: -; Near stub procedure in the prememory segment. Simply perform a -; retn instruction. -; -EXTERN AmdDfltRetPremem:NEAR - -;+--------------------------------------------------------------------------- -; -; myDoReset (Required) -; -; Entry: -; EDX - Reset type -; 1 - Warm reset whenever -; 2 - Cold reset whenever -; 3 - Warm reset immediately -; 4 - Cold reset immediately -; ESI - Pointer to an AMD_CONFIG_PARAMS structure. -; -; Exit: -; EAX - Contains the AGESA_STATUS return code. -; AGESA_SUCCESS The function has completed successfully. -; AGESA_UNSUPPORTED This is a required function, so this -; value being returned causes a critical -; error response value from the AGESA -; software function. -; -; Modified: -; None -; -; Purpose: -; This host environment function must initiate the specified type -; of system reset. -; -; Implementation of this function by the host environment is -; REQUIRED. Some host environments may record this as a request -; allowing other elements in the system to perform some additional -; tasks before the actual reset is issued. -; -; Dependencies: -; The AMD processor contains 3 bits (BiosRstDet[2:0]) in a PCI -; register (F0x6C Link Initialization Control Register) that -; indicate the reset status. These bits are reserved for use by -; the AGESA software and should not be modified by the host -; environment. -; -EXTERN myDoReset:NEAR - - -;+--------------------------------------------------------------------------- -; -; myGetNonVolatileS3Context (Required for proper S3 operation) -; -; Entry: -; None -; -; Exit: -; EBX - Pointer to the non-volatile S3 context block -; ECX - Size in bytes of the non-volatile S3 context block -; -; Modified: -; None -; -; Purpose: -; The host environment must return the pointer to the data -; saved during the mySaveNonVolatileS3Context routine. -; -; Dependencies: -; None -; -EXTERN myGetNonVolatileS3Context:NEAR - - -;---------------------------------------------------------------------------- -; Declare the optional external routines in the prememory segment -;---------------------------------------------------------------------------- - -;+--------------------------------------------------------------------------- -; -; myAgesaHookBeforeExitSelfRefresh (Optional) -; -; Entry: -; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 44h -; ESI - Pointer to a data structure containing the memory information -; -; Exit: -; After returning control to AGESA, AGESA will display: - AGESA_TESTPOINT - 45h -; EAX - Contains the AGESA_STATUS return code -; AGESA_SUCCESS The function has completed successfully -; AGESA_UNSUPPORTED This function is not implemented by the host environment -; AGESA_WARNING A non-critical issue has occued in the host environment -; -; Modified: -; None -; -; Purpose: -; General purpose hook called before the exiting self refresh -; This procedure is called once per channel -; -; Implementation of this function is optional for the host environment -; This call-out is an opportunity for the host environment to make dynamic -; modifications to the memory timing settings specific to the board or host -; environment before exiting self refresh on S3 resume -; -; Dependencies: -; This procedure is called before the exit self refresh bit is set in the resume -; sequence. The host environment must initiate the OS restart process. This procedure -; requires a stack. The host environment must establish the stack environment prior -; to making the call to this procedure -; -EXTERN myAgesaHookBeforeExitSelfRefresh(AmdDfltRetPremem):NEAR - - -;+--------------------------------------------------------------------------- -; -; myHookBeforeDramInit (Optional) -; -; Entry: -; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 40h -; ESI - Pointer to a data structure containing the memory information -; -; Exit: -; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 41h -; EAX - Contains the AGESA_STATUS return code. -; AGESA_SUCCESS The function has completed successfully. -; AGESA_UNSUPPORTED This function is not implemented by the host environment -; -; Modified: -; None -; -; Purpose: -; General-purpose hook called before the DRAM_Init bit is set. Called -; once per MCT -; -; Implementation of this function is optional for the host environment -; This call-out is an opportunity for the host environment to make -; dynamic modifications to the memory timing settings specific to the -; board or host environment -; -; Dependencies: -; None -; -EXTERN myHookBeforeDramInit(AmdDfltRetPremem):NEAR - - -;+--------------------------------------------------------------------------- -; -; myHookBeforeDQSTraining (Optional) -; -; Entry: -; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 42h -; ESI - Pointer to a data structure containing the memory information. -; -; Exit: -; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 43h -; EAX - Contains the AGESA_STATUS return code. -; AGESA_SUCCESS The function has completed successfully. -; AGESA_UNSUPPORTED This function is not implemented by the -; host environment. -; -; Modified: -; None -; -; Purpose: -; General-purpose hook called just before the memory training processes -; begin. Called once per MCT. -; -; Implementation of this function is optional for the host environment. -; This call-out is an opportunity for the host environment to make -; dynamic modifications to the memory timing settings specific to the -; board or host environment. -; -; The host environment may also use this call-out for some board- -; specific features that should be activated at this time point, -; such as: -; Low voltage DIMMs-the host environment should set the recommended -; voltages found in the memory data structure for each memory -; channel. This needs to occur before training begins. -; -; Dependencies: -; None -; -EXTERN myHookBeforeDQSTraining(AmdDfltRetPremem):NEAR - - -;---------------------------------------------------------------------------- -; Define the sample wrapper routines for the prememory segment -;---------------------------------------------------------------------------- - -;+--------------------------------------------------------------------------- -; -; AmdInitEarlyWrapper -; -; Entry: -; On Entry to "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C4h -; DS - 0000 with 4 gigabyte access -; ES - 0000 with 4 gigabyte access -; -; Exit: -; On Exit from "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C5h -; None -; -; Modified: -; None -; -; Purpose: -; A full initialization of the processor is performed. Action details -; differ for the BSP and AP processor cores. -; For the BSP, the following actions are performed: -; Full HyperTransportT link initialization, coherent and non-coherent -; Processor register loading -; Microcode patch load -; Errata workaround processing -; Launch all processor cores -; Configure the processor power management capabilities -; Request a warm reset if needed -; For the AP, the following actions are performed: -; Processor register loading -; Microcode patch load -; Errata workaround processing -; Configure the processor power management capabilities -; -; Dependencies: -; This procedure is expected to be called before main memory initialization -; and before the system warm reset. Prior to this, the basic configuration -; done by the AmdInitReset routine must be completed. -; -; This procedure requires a stack. The host environment must use one of the -; provided service functions to establish the stack environment prior to -; making the call to this procedure. -; -; The processes performed at this time point require communication between -; processor cores. -; -; The host environment must recognize that all processor cores are running -; in parallel and avoid activities that might interfere with the core-to-core -; communication, such as modifying the MTRR settings or writing to the APIC -; registers. -; -AmdInitEarlyWrapper PROC NEAR PUBLIC - local localCfgBlock:AMD_INTERFACE_PARAMS - - pushad - - ; Prepare for the call to create and initialize the input parameters for AmdInitEarly - xor eax, eax - mov ax, ss - shl eax, 4 - lea esi, localCfgBlock - add esi, eax - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 - mov edx, SEG AmdCallout16 - shl edx, 4 - add edx, OFFSET AmdCallout16 - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx - - mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_EARLY - mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap - mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 - push esi - mov dx, SEG AmdCalloutRouterPremem - shl edx, 16 - mov dx, OFFSET AmdCalloutRouterPremem - push edx - call AmdBridge32 - pop edx - - mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr - - ; The structure has been initialized. Now modify the default settings as desired. - - mov edi, esi - add edi, (SIZEOF AMD_CONFIG_PARAMS + (3 * (SIZEOF EXECUTION_CACHE_REGION))) - call oemPlatformConfigInit - - ; Call in to the AmdInitEarly entry point - push edx - call AmdBridge32 - pop edx - - ;; EAX = AGESA_STATUS - ;; AGESA_SUCCESS The function has completed successfully. - ;; AGESA_ALERT An HyperTransportT link CRC error was observed. - ;; AGESA_WARNING One of more of the allocation rules were violated, - ;; but an adjustment was made and space was allocated. - ;; Or a HyperTransport device does not have the expected - ;; capabilities, or unusable redundant HyperTransport - ;; links were found. - ;; AGESA_ERROR One or more of the allocation rules were violated, which - ;; resulted in a requested cache region to not be allocated. - ;; Or, a HyperTransport device failed to initialize. - ;; AGESA_CRITICAL An illegal or unsupported mixture of processor types was - ;; found, or the processors installed were found to have an - ;; insufficient MP capability rating for this platform. - - .if (eax != AGESA_SUCCESS) - mov al, (AMD_EARLY_PARAMS ptr [esi]).StdHeader.HeapStatus - mov ebx, AGESA_B2_ADDRESS - call AmdProcessAgesaErrors - .endif - - ; Allow AGESA to free the space used by AmdInitEarly - pop esi - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT - call AmdBridge32 - - - popad - ret -AmdInitEarlyWrapper ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdInitPostWrapper -; -; Entry: -; On Entry to "AmdInitPost" AGESA will display AGESA_TESTPOINT - C6h -; DS - 0000 with 4 gigabyte access -; ES - 0000 with 4 gigabyte access -; -; Exit: -; On Exit from "AmdInitPost" AGESA will display AGESA_TESTPOINT - C7h -; None -; -; Modified: -; None -; -; Purpose: -; The main system memory is located, initialized, and brought on-line. -; The processor(s) are prepared for full operation and control by the -; host environment. Action details differ for the BSP and AP processor -; cores. -; For the BSP, the following actions are performed: -; Full memory initialization and configuration. BSP is the master for -; this process and may delegate some tasks to APs. -; AP collection of data for use later. -; Transfer the HOBs including the artifact data out of the pre-memory -; cache storage into a temporary holding buffer in the main memory. -; Check the BIST status of the BSP -; Shut down the APs. -; Prepare for the host environment to begin main boot activity. -; Disable the pre-memory stack. -; For the APs, the following actions are performed: -; Report core identity information. -; Execute indicated memory initialization processes as directed. -; Check the BIST status of the AP -; Disable the pre-memory stack. -; Prepare to halt, giving control to host environment. -; The entire range of system memory is enabled for Write-Back cache. -; The fixed MTRRs and the variable MTRRs[7:6] are not changed in order -; to leave in place any flash ROM region currently set for Write-Protect -; execution cache. -; -; Dependencies: -; This procedure is called after the host environment has determined that -; a normal boot to operating system should be performed after any system -; warm reset is completed and after the configuration done by AmdInitEarly -; has completed. -; -; This procedure requires a stack. The host environment must use one of the -; provided service functions to establish the stack environment prior to -; making the call to this procedure. -; -; The processes performed at this time point require communication between -; processor cores. The host environment must recognize that all processor -; cores are running in parallel and avoid activities that might interfere -; with the core-to-core communication, such as modifying the MTRR settings -; or writing to the APIC registers. -; -AmdInitPostWrapper PROC NEAR PUBLIC - local localCfgBlock:AMD_INTERFACE_PARAMS - - pushad - - ; Prepare for the call to create and initialize the input parameters for AmdInitPost - xor eax, eax - mov ax, ss - shl eax, 4 - lea esi, localCfgBlock - add esi, eax - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 - mov edx, SEG AmdCallout16 - shl edx, 4 - add edx, OFFSET AmdCallout16 - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx - - mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_POST - mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap - mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 - push esi - mov dx, SEG AmdCalloutRouterPremem - shl edx, 16 - mov dx, OFFSET AmdCalloutRouterPremem - push edx - call AmdBridge32 - pop edx - - mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr - - ; The structure has been initialized. Now modify the default settings as desired. - - mov edi, esi - add edi, SIZEOF AMD_CONFIG_PARAMS - call oemPlatformConfigInit - - ; Call in to the AmdInitPost entry point - push edx - call AmdBridge32 - pop edx - - ;; EAX = AGESA_STATUS - ;; AGESA_SUCCESS The function has completed successfully. - ;; AGESA_ALERT A BIST error was found on one of the cores. - ;; AGESA_WARNING HT Assist feature is running sub-optimally. - ;; AGESA_FATAL Memory initialization failed. - - .if (eax != AGESA_SUCCESS) - mov al, (AMD_POST_PARAMS ptr [esi]).StdHeader.HeapStatus - mov ebx, AGESA_B2_ADDRESS - call AmdProcessAgesaErrors - .endif - - ; Allow AGESA to free the space used by AmdInitPost - pop esi - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT - call AmdBridge32 - - - popad - ret -AmdInitPostWrapper ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdInitResumeWrapper -; -; Entry: -; On Entry to "AmdInitResume" AGESA will display AGESA_TESTPOINT - D0h -; DS - 0000 with 4 gigabyte access -; ES - 0000 with 4 gigabyte access -; -; Exit: -; On Exit from "AmdInitResume" AGESA will display AGESA_TESTPOINT - D1h -; None -; -; Modified: -; None -; -; Purpose: -; This procedure initializes or re-initializes the silicon components -; for the resume boot path. For the processor, main memory is brought -; out of self-refresh mode. This procedure will use the context data -; in the NvStorage area of the input structure to re-start the main -; memory. The host environment must fill the AMD_S3_PARAMS NvStorage -; and VolatileStorage pointers and related size elements to describe -; the location of the context data. Note that for this procedure, the -; two data areas do not need to be contained in one buffer zone, they -; can be anywhere in the accessible memory address space. If the host -; environment uses a non-volatile storage device accessed on the system -; address bus such as flashROM, then the context data does not need to -; be moved prior to this call. If the host environment uses a non- -; volatile storage device not located on the system address bus (e.g. -; CMOS or SSEPROM) then the host environment must transfer the context -; data to a buffer in main memory prior to calling this procedure. -; -; Dependencies: -; The host environment must have determined that the system should take -; the resume path prior to calling this procedure. The configuration -; done by AmdInitEarly and any necessary warm reset must be complete. -; After this procedure, execution proceeds to general system restoration. -; -; This procedure requires a stack. The host environment must use one of -; the provided service functions to establish the stack environment prior -; to making the call to this procedure. -; -AmdInitResumeWrapper PROC NEAR PUBLIC - local localCfgBlock:AMD_INTERFACE_PARAMS - - pushad - - ; Prepare for the call to create and initialize the input parameters for AmdInitResume - xor eax, eax - mov ax, ss - shl eax, 4 - lea esi, localCfgBlock - add esi, eax - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 - mov edx, SEG AmdCallout16 - shl edx, 4 - add edx, OFFSET AmdCallout16 - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx - - mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESUME - mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap - mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 - push esi - mov dx, SEG AmdCalloutRouterPremem - shl edx, 16 - mov dx, OFFSET AmdCalloutRouterPremem - push edx - call AmdBridge32 - pop edx - - mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr - - ; The structure has been initialized. Now modify the default settings as desired. - - mov edi, esi - add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS) - call oemPlatformConfigInit - - call myGetNonVolatileS3Context - mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorage, ebx - mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorageSize, ecx - - ; Call in to the AmdInitResume entry point - push edx - call AmdBridge32 - pop edx - - ;; EAX = AGESA_STATUS - ;; AGESA_SUCCESS Re-initialization has been completed successfully. - .if (eax != AGESA_SUCCESS) - mov al, (AMD_RESUME_PARAMS ptr [esi]).StdHeader.HeapStatus - mov ebx, AGESA_B2_ADDRESS - call AmdProcessAgesaErrors - .endif - - - ; Allow AGESA to free the space used by AmdInitResume - pop esi - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT - call AmdBridge32 - - - popad - ret -AmdInitResumeWrapper ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdCalloutRouterPremem -; -; Entry: -; ECX - Callout function number -; EDX - Function-specific UINTN -; ESI - Pointer to function specific data -; -; Exit: -; EAX - Contains the AGESA_STATUS return code. -; -; Modified: -; None -; -; Purpose: -; The call out router function for AmdInitEarly, -; AmdInitPost, and AmdInitResume. -; -; Dependencies: -; None -; -AmdCalloutRouterPremem PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES - xor ax, ax - mov ds, ax - mov es, ax - lea di, cs:CalloutRouterTablePremem - mov eax, AGESA_UNSUPPORTED - -loopThruTable: - cmp di, OFFSET cs:CalloutRouterTablePrememEnd - jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED - cmp ecx, cs:[di].sOemCallout.FuncName - je FoundMatch - add di, SIZEOF sOemCallout - jmp loopThruTable - -FoundMatch: - mov bx, cs:[di].sOemCallout.FuncPtr - call bx - -amdCpuCalloutExit: - ret -AmdCalloutRouterPremem ENDP - - -;---------------------------------------------------------------------------- -; Define the callout dispatch table for the prememory segment -;---------------------------------------------------------------------------- - -CalloutRouterTablePremem LABEL BYTE - ;; Add entries as desired. - sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDPremem> - sOemCallout <AGESA_HOOKBEFORE_DRAM_INIT, OFFSET myHookBeforeDramInit> - sOemCallout <AGESA_HOOKBEFORE_DQS_TRAINING, OFFSET myHookBeforeDQSTraining> - sOemCallout <AGESA_HOOKBEFORE_EXIT_SELF_REF, OFFSET myAgesaHookBeforeExitSelfRefresh> - sOemCallout <AGESA_DO_RESET, OFFSET myDoReset> -CalloutRouterTablePrememEnd LABEL BYTE - - - -AMD_PREMEM_END - - -;---------------------------------------------------------------------------- -; POST SEGMENT -; This segment may be decompressed and run from system RAM. -;---------------------------------------------------------------------------- - -AMD_POST_START - - -;---------------------------------------------------------------------------- -; Declare the external routines required in the POST segment -;---------------------------------------------------------------------------- - -;+--------------------------------------------------------------------------- -; -; myAllocateBuffer (Required) -; -; Entry: -; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E2h -; ESI - Pointer to an AGESA_BUFFER_PARAMS structure. -; -; typedef struct { -; IN OUT AMD_CONFIG_PARAMS StdHeader; -; IN UINT32 BufferLength; -; IN UINT32 BufferHandle; -; OUT VOID *BufferPointer; -; } AGESA_BUFFER_PARAMS; -; -; Exit: -; After this hook, AGESA will display - AGESA_TESTPOINT - E3h -; EAX - Contains the AGESA_STATUS return code. -; AGESA_SUCCESS The requested size of memory has been -; successfully allocated. -; AGESA_UNSUPPORTED This is a required function, so this -; value being returned causes a critical -; error response value from the AGESA -; software function. -; AGESA_ERROR Less than the requested amount of memory -; was allocated. -; -; Modified: -; EAX -; -; Purpose: -; This function is used after main memory has been initialized -; and the host environment has taken control of memory allocation. -; This function must allocate a buffer of the requested size or -; larger. This function is required to be implemented by the host -; environment. -; -; Dependencies: -; The following call-outs must work together in the host system. -; Parameters of the same name have the same function and must be -; treated the same in each function: -; AgesaAllocateBuffer -; AgesaDeallocateBuffer -; AgesaLocateBuffer -; AgesaRunFcnOnAp -; The host environment may need to reserve a location in the buffer -; to store any host environment specific value(s). The returned -; pointer must not include this reserved space. The host environment -; on the AgesaDeallocateBuffer call needs to account for the reserved -; space. This reserved space may be an identifier or the "handle" -; used to identify the specific memory block. -; -EXTERN myAllocateBuffer:NEAR - -;+--------------------------------------------------------------------------- -; -; myDeallocateBuffer (Required) -; -; Entry: -; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E4h -; ESI - Pointer to an AGESA_BUFFER_PARAMS structure. -; -; typedef struct { -; IN OUT AMD_CONFIG_PARAMS StdHeader; -; IN UINT32 BufferLength; -; IN UINT32 BufferHandle; -; OUT VOID *BufferPointer; -; } AGESA_BUFFER_PARAMS; -; -; Exit: -; After this hook, AGESA will display - AGESA_TESTPOINT - E5h -; EAX - Contains the AGESA_STATUS return code. -; AGESA_SUCCESS The function has completed successfully. -; AGESA_BOUNDS_CHK The BufferHandle is invalid. The AGESA -; software continues with its function. -; AGESA_UNSUPPORTED This is a required function, so this -; value being returned causes a critical -; error response value from the AGESA -; software function. -; -; Modified: -; EAX -; -; Purpose: -; This function is used after main memory has been initialized -; and the host environment has taken control of memory allocation. -; This function releases a valid working buffer. This function is -; required for the host environment to implement. -; -; Dependencies: -; The following call-outs must work together in the host system. -; Parameters of the same name have the same function and must be -; treated the same in each function: -; AgesaAllocateBuffer -; AgesaDeallocateBuffer -; AgesaLocateBuffer -; AgesaRunFcnOnAp -; -EXTERN myDeallocateBuffer:NEAR - -;+--------------------------------------------------------------------------- -; -; myLocateBuffer (Required) -; -; Entry: -; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E6h -; ESI - Pointer to an AGESA_BUFFER_PARAMS structure. -; -; typedef struct { -; IN OUT AMD_CONFIG_PARAMS StdHeader; -; IN UINT32 BufferLength; -; IN UINT32 BufferHandle; -; OUT VOID *BufferPointer; -; } AGESA_BUFFER_PARAMS; -; -; Exit: -; After this hook, AGESA will display - AGESA_TESTPOINT - E7h -; EAX - Contains the AGESA_STATUS return code. -; AGESA_SUCCESS The function has completed successfully. -; AGESA_BOUNDS_CHK The presented handle is invalid or the -; buffer could not be located. -; -; Modified: -; EAX -; -; Purpose: -; This function is used after main memory has been initialized -; and the host environment has taken control of memory allocation. -; This function must locate the buffer related to the indicated -; handle and return the address of the buffer and its length. -; This function is required to be implemented in the host -; environment. -; -; Dependencies: -; The following call-outs must work together in the host system. -; Parameters of the same name have the same function and must be -; treated the same in each function: -; AgesaAllocateBuffer -; AgesaDeallocateBuffer -; AgesaLocateBuffer -; AgesaRunFcnOnAp -; -EXTERN myLocateBuffer:NEAR - - -;+--------------------------------------------------------------------------- -; -; myRunFuncOnAp (Required) -; -; Entry: -; EDX - Local APIC ID of the target core. -; -; Exit: -; None -; -; Modified: -; None -; -; Purpose: -; The host environment must route execution to the target AP and -; have that AP call the AmdLateRunApTaskWrapper routine defined -; above. -; -; Dependencies: -; None -; -EXTERN myRunFuncOnAp:NEAR - -;+--------------------------------------------------------------------------- -; -; mySaveNonVolatileS3Context (Required for proper S3 operation) -; -; Entry: -; EBX - Pointer to the non-volatile S3 context block -; ECX - Size in bytes of the non-volatile S3 context block -; -; Exit: -; None -; -; Modified: -; None -; -; Purpose: -; The host environment must save the non-volatile data to an area -; that will not lose context while in the ACPI S3 sleep state, but -; cannot be placed in system RAM. This data will need to be -; available during the call to AmdInitResume. -; -; Dependencies: -; None -; -EXTERN mySaveNonVolatileS3Context:NEAR - -;+--------------------------------------------------------------------------- -; -; mySaveVolatileS3Context (Required for proper S3 operation) -; -; Entry: -; EBX - Pointer to the volatile S3 context block -; ECX - Size in bytes of the volatile S3 context block -; -; Exit: -; None -; -; Modified: -; None -; -; Purpose: -; The host environment must save the volatile data to an area -; that will not lose context while in the ACPI S3 sleep state. -; This data will need to be available during the call to -; AmdS3LateRestore. -; -; Dependencies: -; None -; -EXTERN mySaveVolatileS3Context:NEAR - -;+--------------------------------------------------------------------------- -; -; myGetVolatileS3Context (Required for proper S3 operation) -; -; Entry: -; None -; -; Exit: -; EBX - Pointer to the volatile S3 context block -; ECX - Size in bytes of the volatile S3 context block -; -; Modified: -; None -; -; Purpose: -; The host environment must return the pointer to the data -; saved during the mySaveVolatileS3Context routine. -; -; Dependencies: -; None -; -EXTERN myGetVolatileS3Context:NEAR - - -;---------------------------------------------------------------------------- -; Define the sample wrapper routines for the POST segment -;---------------------------------------------------------------------------- - -;+--------------------------------------------------------------------------- -; -; AmdInitEnvWrapper -; -; Entry: -; On Entry to "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C8h -; DS - 0000 with 4 gigabyte access -; ES - 0000 with 4 gigabyte access -; -; Exit: -; On Exit from "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C9h -; None -; -; Modified: -; None -; -; Purpose: -; This procedure uses the AgesaAllocateBuffer call-out to acquire -; permanent buffer space for the UEFI Hand-Off Blocks (HOBs). This -; is also known as, or includes, artifact data being used by the -; AGESA software. Upon entry to this procedure, the data is being -; held in a temporary memory location and it must be moved to a -; location controlled and protected by the host environment. -; -; These actions are performed by the BSP. The APs are not assigned -; any tasks at this time point. -; -; Dependencies: -; This procedure must be called after full memory is initialized and -; the host environment has taken control of main memory allocation. -; This procedure should be called before the PCI enumeration takes -; place and as soon as possible after the host environment memory -; allocation sub-system has started. -; -; This procedure requires a stack. The host environment must use one -; of the provided service functions to establish the stack environment -; prior to making the call to this procedure. -; -AmdInitEnvWrapper PROC NEAR PUBLIC - local localCfgBlock:AMD_INTERFACE_PARAMS - - pushad - - ; Prepare for the call to create and initialize the input parameters for AmdInitEnv - xor eax, eax - mov ax, ss - shl eax, 4 - lea esi, localCfgBlock - add esi, eax - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 - mov edx, SEG AmdCallout16 - shl edx, 4 - add edx, OFFSET AmdCallout16 - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx - - mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_ENV - mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram - mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 - push esi - mov dx, SEG AmdCalloutRouterPost - shl edx, 16 - mov dx, OFFSET AmdCalloutRouterPost - push edx - call AmdBridge32 - pop edx - - mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr - - ; The structure has been initialized. Now modify the default settings as desired. - - mov edi, esi - add edi, SIZEOF AMD_CONFIG_PARAMS - call oemPlatformConfigInit - - ; Call in to the AmdInitEnv entry point - push edx - call AmdBridge32 - pop edx - - ;; EAX = AGESA_STATUS - ;; AGESA_SUCCESS The function has completed successfully. - ;; AGESA_ERROR The artifact data could not be found or the host - ;; environment failed to allocate sufficient buffer space. - - .if (eax != AGESA_SUCCESS) - mov al, (AMD_ENV_PARAMS ptr [esi]).StdHeader.HeapStatus - mov ebx, AGESA_B2_ADDRESS - call AmdProcessAgesaErrors - .endif - - ; Allow AGESA to free the space used by AmdInitEnv - pop esi - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT - call AmdBridge32 - - - popad - ret -AmdInitEnvWrapper ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdInitMidWrapper -; -; Entry: -; On Entry to "AmdInitMid" AGESA will display AGESA_TESTPOINT - CAh -; DS - 0000 with 4 gigabyte access -; ES - 0000 with 4 gigabyte access -; -; Exit: -; On Exit from "AmdInitMid" AGESA will display AGESA_TESTPOINT - CBh -; None -; -; Modified: -; None -; -; Purpose: -; This procedure call performs special configuration requirements for -; the graphics display hardware. -; -; These actions are performed by the BSP. The APs are not assigned any -; tasks at this time point. -; -; Dependencies: -; This procedure must be called after PCI enumeration has allocated -; resources, but before the video BIOS call is performed. -; -; This procedure requires a stack. The host environment must use one -; of the provided service functions to establish the stack environment -; prior to making the call to this procedure. -; -AmdInitMidWrapper PROC NEAR PUBLIC - local localCfgBlock:AMD_INTERFACE_PARAMS - - pushad - - ; Prepare for the call to create and initialize the input parameters for AmdInitMid - xor eax, eax - mov ax, ss - shl eax, 4 - lea esi, localCfgBlock - add esi, eax - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 - mov edx, SEG AmdCallout16 - shl edx, 4 - add edx, OFFSET AmdCallout16 - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx - - mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_MID - mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram - mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 - push esi - mov dx, SEG AmdCalloutRouterPost - shl edx, 16 - mov dx, OFFSET AmdCalloutRouterPost - push edx - call AmdBridge32 - pop edx - - mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr - - ; The structure has been initialized. Now modify the default settings as desired. - - mov edi, esi - add edi, SIZEOF AMD_CONFIG_PARAMS - call oemPlatformConfigInit - - ; Call in to the AmdInitMid entry point - push edx - call AmdBridge32 - pop edx - - ;; EAX = AGESA_STATUS - ;; AGESA_SUCCESS The function has completed successfully. - - .if (eax != AGESA_SUCCESS) - mov al, (AMD_MID_PARAMS ptr [esi]).StdHeader.HeapStatus - mov ebx, AGESA_B2_ADDRESS - call AmdProcessAgesaErrors - .endif - - ; Allow AGESA to free the space used by AmdInitMid - pop esi - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT - call AmdBridge32 - - - popad - ret - -AmdInitMidWrapper ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdInitLateWrapper -; -; Entry: -; On Entry to "AmdInitLate" AGESA will display AGESA_TESTPOINT - CCh -; DS - 0000 with 4 gigabyte access -; ES - 0000 with 4 gigabyte access -; -; Exit: -; On Exit from "AmdInitLate" AGESA will display AGESA_TESTPOINT - CDh -; None -; -; Modified: -; None -; -; Purpose: -; The main purpose of this function is to generate informational -; data tables used by the operating system. The individual tables -; can be selected for generation through the user selection entries -; on the input parameters. -; -; This routine uses the Call-Out AgesaAllocateBuffer to allocate a -; buffer of the proper size to contain the data. -; -; The code path separates the BSP from the APs and perform a separate -; and appropriate list of tasks for each class of core. -; For the BSP, the following actions are performed: -; Allocate buffer space for the tables. -; Generate the table contents. -; Make sure that the CPU is in a known good power state before -; proceeding to boot the OS. -; For the APs, the following actions are performed: -; Final register settings preparing for entry to OS. -; Establish the final PState for entry to OS. -; -; Dependencies: -; This routine is expected to be executed late in the boot sequence -; after main memory has been initialized, after PCI enumeration has -; completed, after the host environment ACPI sub-system has started, -; after the host environment has taken control of the APs, but just -; before the start of OS boot. -; -; The host environment must provide the required call-outs listed in -; the "Required Call-Out Procedures" section of the AGESA interface -; specification to provide the buffer space in main memory and execute -; code on the APs. The host environment must register the created ACPI -; table in the main ACPI pointer tables. This may require moving the -; generated tables to another location in memory. -; -; This procedure requires a stack. The host environment must establish -; the stack environment prior to making the call to this procedure. -; Some functions depend upon the preservation of the heap data across -; the shift from pre-memory environment to a post-memory environment. -; If that data was not preserved, then those functions cannot complete -; and an error is returned. -; -AmdInitLateWrapper PROC NEAR PUBLIC - local localCfgBlock:AMD_INTERFACE_PARAMS - - pushad - - ; Prepare for the call to create and initialize the input parameters for AmdInitLate - xor eax, eax - mov ax, ss - shl eax, 4 - lea esi, localCfgBlock - add esi, eax - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 - mov edx, SEG AmdCallout16 - shl edx, 4 - add edx, OFFSET AmdCallout16 - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx - - mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_LATE - mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram - mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 - push esi - mov dx, SEG AmdCalloutRouterPost - shl edx, 16 - mov dx, OFFSET AmdCalloutRouterPost - push edx - call AmdBridge32 - pop edx - - mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr - - ; The structure has been initialized. Now modify the default settings as desired. - - mov edi, esi - add edi, SIZEOF AMD_CONFIG_PARAMS - call oemPlatformConfigInit - - ; Call in to the AmdInitLate entry point - push edx - call AmdBridge32 - pop edx - - ;; EAX = AGESA_STATUS - ;; AGESA_SUCCESS The function has completed successfully. - ;; AGESA_ALERT - ;; AGESA_ERROR The system could not allocate the needed amount of - ;; buffer space; or could not locate the artifact data block in - ;; memory. Likely cause: the host environment may not have preserved - ;; the data properly. - - .if (eax != AGESA_SUCCESS) - mov al, (AMD_LATE_PARAMS ptr [esi]).StdHeader.HeapStatus - mov ebx, AGESA_B2_ADDRESS - call AmdProcessAgesaErrors - .endif - - push es - mov ax, SEG AmdAcpiSratPointer - mov es, ax - - mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSrat - mov es:AmdAcpiSratPointer, ebx - mov eax, DWORD PTR [ebx + 4] - mov es:AmdAcpiSratSize, eax - - mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSlit - mov es:AmdAcpiSlitPointer, ebx - mov eax, DWORD PTR [ebx + 4] - mov es:AmdAcpiSlitSize, eax - - mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiPState - mov es:AmdAcpiSsdtPointer, ebx - mov eax, DWORD PTR [ebx + 4] - mov es:AmdAcpiSsdtSize, eax - - xor eax, eax - - mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce - mov es:AmdAcpiWheaMcePointer, ebx - mov ax, WORD PTR [ebx] - mov es:AmdAcpiWheaMceSize, eax - - mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce - mov es:AmdAcpiWheaCmcPointer, ebx - mov ax, WORD PTR [ebx] - mov es:AmdAcpiWheaCmcSize, eax - - mov eax, (AMD_LATE_PARAMS ptr [esi]).DmiTable - mov es:AmdDmiInfoPointer, eax - pop es - - - ; Allow AGESA to free the space used by AmdInitLate - pop esi - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT - call AmdBridge32 - - popad - ret - -AmdInitLateWrapper ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdS3SaveWrapper -; -; Entry: -; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CEh -; DS - 0000 with 4 gigabyte access -; ES - 0000 with 4 gigabyte access -; -; Exit: -; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CFh -; None -; -; Modified: -; None -; -; Purpose: -; This procedure saves critical registers and/or configuration -; information for preservation across a system suspend mode. All -; actions needed to prepare the processor for suspend mode is -; performed, however this procedure does NOT initiate the suspend -; process. The host environment is expected to perform that duty. -; -; These actions are performed by the BSP. The APs are not assigned -; any tasks at this time point. -; -; The initializer routine will NULL out the save area pointers and -; sizes. This procedure will determine the size of storage needed -; for all the processor context, and make a call out to the environment -; for allocation of one buffer to store all of the data. Upon exit, the -; pointers and sizes within the AMD_S3_PARAMS structure will be updated -; with the appropriate addresses within the buffer that was allocated. -; The host environment is expected to then transfer the data pointed to -; by NvStorage to a non-volatile storage area, and the data pointed to -; by VolatileStorage to either a non-volatile storage area or system -; RAM that retains its content across suspend. -; -; Dependencies: -; The host environment must initiate the suspend process. -; -; This procedure requires a stack. The host environment must establish -; the stack environment prior to making the call to this procedure. -; -AmdS3SaveWrapper PROC NEAR PUBLIC - local localCfgBlock:AMD_INTERFACE_PARAMS - - pushad - - ; Prepare for the call to create and initialize the input parameters for AmdS3Save - xor eax, eax - mov ax, ss - shl eax, 4 - lea esi, localCfgBlock - add esi, eax - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 - mov edx, SEG AmdCallout16 - shl edx, 4 - add edx, OFFSET AmdCallout16 - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx - - mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3_SAVE - mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram - mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 - push esi - mov dx, SEG AmdCalloutRouterPost - shl edx, 16 - mov dx, OFFSET AmdCalloutRouterPost - push edx - call AmdBridge32 - pop edx - - mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr - - ; The structure has been initialized. Now modify the default settings as desired. - - mov edi, esi - add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS) - call oemPlatformConfigInit - - ; Call in to the AmdS3Save entry point - push edx - call AmdBridge32 - pop edx - - ;; EAX = AGESA_STATUS - ;; AGESA_SUCCESS All suspend duties have been completed successfully. - - .if (eax != AGESA_SUCCESS) - mov al, (AMD_S3SAVE_PARAMS ptr [esi]).StdHeader.HeapStatus - mov ebx, AGESA_B2_ADDRESS - call AmdProcessAgesaErrors - .endif - - mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorageSize - .if (ecx != 0) - mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorage - call mySaveNonVolatileS3Context - .endif - - mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize - .if (ecx != 0) - mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage - call mySaveVolatileS3Context - .endif - - ; Allow AGESA to free the space used by AmdS3Save - pop esi - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT - call AmdBridge32 - - popad - ret - -AmdS3SaveWrapper ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdS3LateRestoreWrapper -; -; Entry: -; On Entry to "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D2h -; DS - 0000 with 4 gigabyte access -; ES - 0000 with 4 gigabyte access -; -; Exit: -; On Exit from "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D3h -; None -; -; Modified: -; None -; -; Purpose: -; This procedure restores the processor state, reloads critical -; silicon component registers, and performs any re-initialization -; required by the silicon. This procedure will use the context data -; in the VolatileStorage area of the input structure to restore the -; processor registers. -; -; The host environment must fill the AMD_S3_PARAMS NvStorage and -; VolatileStorage pointers and related size elements to describe -; the location of the context data. Note that for this procedure, -; the two data areas do not need to be contained in one buffer zone, -; they can be anywhere in the accessible memory address space. If -; the host environment uses a non-volatile storage device accessed -; on the system address bus such as flashROM, then the context data -; does not need to be moved prior to this call. If the host -; environment uses a non-volatile storage device not located on the -; system address bus (e.g. CMOS or SSEPROM) then the host environment -; must transfer the context data to a buffer in main memory prior to -; calling this procedure. -; -; These actions are performed by the BSP. The APs are not assigned -; any tasks at this time point. -; -; Dependencies: -; This procedure is called late in the resume sequence, after the -; PCI control space is restored and just before resuming operating -; system execution. -; -; The host environment must initiate the OS restart process. -; -; This procedure requires a stack. The host environment must establish -; the stack environment prior to making the call to this procedure. -; -AmdS3LateRestoreWrapper PROC NEAR PUBLIC - local localCfgBlock:AMD_INTERFACE_PARAMS - - pushad - - ; Prepare for the call to create and initialize the input parameters for AmdS3LateRestore - xor eax, eax - mov ax, ss - shl eax, 4 - lea esi, localCfgBlock - add esi, eax - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 - mov edx, SEG AmdCallout16 - shl edx, 4 - add edx, OFFSET AmdCallout16 - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx - - mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3LATE_RESTORE - mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram - mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 - push esi - mov dx, SEG AmdCalloutRouterPost - shl edx, 16 - mov dx, OFFSET AmdCalloutRouterPost - push edx - call AmdBridge32 - pop edx - - mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr - - ; The structure has been initialized. Now modify the default settings as desired. - - mov edi, esi - add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS) - call oemPlatformConfigInit - - call myGetVolatileS3Context - mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage, ebx - mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize, ecx - - ; Call in to the AmdS3LateRestore entry point - push edx - call AmdBridge32 - pop edx - - ;; EAX = AGESA_STATUS - ;; AGESA_SUCCESS All resume processes have been completed successfully. - - .if (eax != AGESA_SUCCESS) - mov al, (AMD_S3LATE_PARAMS ptr [esi]).StdHeader.HeapStatus - mov ebx, AGESA_B2_ADDRESS - call AmdProcessAgesaErrors - .endif - - ; Allow AGESA to free the space used by AmdS3LateRestore - pop esi - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT - call AmdBridge32 - - popad - ret -AmdS3LateRestoreWrapper ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdLateRunApTaskWrapper -; -; Entry: -; Prior to this hook, AGESA will display - AGESA_TESTPOINT - D4h -; DS - 0000 with 4 gigabyte access -; ES - 0000 with 4 gigabyte access -; -; Exit: -; After this hook, AGESA will display - AGESA_TESTPOINT - D5h -; None -; -; Modified: -; None -; -; Purpose: -; This entry point is tightly connected with the "AgesaRunFcnOnAp" -; call out. The AGESA software will call the call-out "AgesaRunFcnOnAp"; -; the host environment will then call this entry point to have the AP -; execute the requested function. This is needed late in the Post and -; Resume branches for running an AP task since the AGESA software has -; relinquished control of the APs to the host environment. -; -; Dependencies: -; The host environment must implement the"AgesaRunFcnOnAp" call-out -; and route execution to the target AP. -; -AmdLateRunApTaskWrapper PROC NEAR PUBLIC - local localCfgBlock:AMD_INTERFACE_PARAMS - - pushad - - ; Prepare for the call to create and initialize the input parameters for AmdLateRunApTask - xor eax, eax - mov ax, ss - shl eax, 4 - lea esi, localCfgBlock - add esi, eax - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 - mov edx, SEG AmdCallout16 - shl edx, 4 - add edx, OFFSET AmdCallout16 - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx - - mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_LATE_RUN_AP_TASK - mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram - mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 - push esi - mov dx, SEG AmdCalloutRouterPost - shl edx, 16 - mov dx, OFFSET AmdCalloutRouterPost - push edx - call AmdBridge32 - pop edx - - mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr - - ; The structure has been initialized. Now modify the default settings as desired. - - push es - mov ax, SEG AmdRunCodeOnApDataPointer - mov es, ax - mov eax, es:AmdRunCodeOnApDataPointer - mov (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock, eax - mov eax, es:AmdRunCodeOnApDataSize - mov (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength, eax - mov eax, es:AmdRunCodeOnApFunction - mov (AP_EXE_PARAMS PTR [esi]).FunctionNumber, eax - pop es - - ; Call in to the AmdLateRunApTask dispatcher - push edx - call AmdBridge32 - pop edx - - ;; EAX = AGESA_STATUS - push es - mov bx, SEG AmdRunCodeOnApStatus - mov es, bx - mov es:AmdRunCodeOnApStatus, eax - pop es - - ; Allow AGESA to free the space used by AmdLateRunApTask - pop esi - mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT - call AmdBridge32 - - popad - ret - -AmdLateRunApTaskWrapper ENDP - - -;+--------------------------------------------------------------------------- -; -; AmdRunFuncOnAp (Required) -; -; Entry: -; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E8h -; EDX - Local APIC ID of the target core. -; ESI - Pointer to an AP_EXE_PARAMS structure. -; -; typedef struct { -; IN OUT AMD_CONFIG_PARAMS StdHeader; -; IN UINT32 FunctionNumber; -; IN VOID *RelatedDataBlock; -; IN UINT32 RelatedDataBlockLength; -; } AP_EXE_PARAMS; -; -; Exit: -; After this hook, AGESA will display - AGESA_TESTPOINT - E9h -; EAX - Contains the AGESA_STATUS return code. -; AGESA_SUCCESS The function has completed successfully. -; AGESA_UNSUPPORTED This is a required function, so this value -; being returned causes a critical error -; response value from the AGESAT software -; function and no memory initialized. -; AGESA_WARNING The AP did not respond. -; -; Modified: -; EAX -; -; Purpose: -; This function is used after main memory has been initialized -; and the host environment has taken control of AP task dispatching. -; This function must cause the indicated function code to be executed -; upon the specified Application Processor. This procedure must be -; executed in 32-bit mode. This function is required to be implemented -; in the host environment. -; -; Dependencies: -; The host environment must route execution to the target AP and -; have that AP call the"AmdLateRunApTask" entry point. -; -AmdRunFuncOnAp PROC NEAR PUBLIC - - push es - mov ax, SEG AmdRunCodeOnApDataPointer - mov es, ax - mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock - mov es:AmdRunCodeOnApDataPointer, eax - mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength - mov es:AmdRunCodeOnApDataSize, eax - mov eax, (AP_EXE_PARAMS PTR [esi]).FunctionNumber - mov es:AmdRunCodeOnApFunction, eax - mov eax, AGESA_UNSUPPORTED - mov es:AmdRunCodeOnApStatus, eax - pop es - - call myRunFuncOnAp - - push es - mov ax, SEG AmdRunCodeOnApStatus - mov es, ax - mov eax, es:AmdRunCodeOnApStatus - pop es - ret -AmdRunFuncOnAp ENDP - - - -;+--------------------------------------------------------------------------- -; -; AmdCalloutRouterPost -; -; Entry: -; ECX - Callout function number -; EDX - Function-specific UINTN -; ESI - Pointer to function specific data -; -; Exit: -; EAX - Contains the AGESA_STATUS return code. -; -; Modified: -; None -; -; Purpose: -; The call out router function for AmdInitEnv, -; AmdInitMid, AmdInitLate, AmdS3Save, and -; AmdS3LateRestore. -; -; Dependencies: -; None -; -AmdCalloutRouterPost PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES - xor ax, ax - mov ds, ax - mov es, ax - lea di, cs:CalloutRouterTablePost - mov eax, AGESA_UNSUPPORTED - -loopThruTable: - cmp di, OFFSET cs:CalloutRouterTablePostEnd - jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED - cmp ecx, cs:[di].sOemCallout.FuncName - je FoundMatch - add di, SIZEOF sOemCallout - jmp loopThruTable - -FoundMatch: - mov bx, cs:[di].sOemCallout.FuncPtr - call bx - -amdCpuCalloutExit: - ret -AmdCalloutRouterPost ENDP - - -;---------------------------------------------------------------------------- -; Define the callout dispatch table for the POST segment -;---------------------------------------------------------------------------- - -CalloutRouterTablePost LABEL BYTE - ;; Add entries as desired. - sOemCallout <AGESA_ALLOCATE_BUFFER, OFFSET myAllocateBuffer> - sOemCallout <AGESA_DEALLOCATE_BUFFER, OFFSET myDeallocateBuffer> - sOemCallout <AGESA_LOCATE_BUFFER, OFFSET myLocateBuffer> - sOemCallout <AGESA_RUNFUNC_ONAP, OFFSET AmdRunFuncOnAp> -CalloutRouterTablePostEnd LABEL BYTE - -AMD_POST_END - - -;---------------------------------------------------------------------------- -; CPU DATA SEGMENT -; This segment must be writable, and present at the time that -; AmdInitLate is run. -;---------------------------------------------------------------------------- - -CPU_DATASEG_START - - ;; Data used to store pointers for later use by the host environment. - PUBLIC AmdAcpiSratPointer - PUBLIC AmdAcpiSratSize - PUBLIC AmdAcpiSlitPointer - PUBLIC AmdAcpiSlitSize - PUBLIC AmdAcpiSsdtPointer - PUBLIC AmdAcpiSsdtSize - PUBLIC AmdAcpiWheaMcePointer - PUBLIC AmdAcpiWheaMceSize - PUBLIC AmdAcpiWheaCmcPointer - PUBLIC AmdAcpiWheaCmcSize - PUBLIC AmdDmiInfoPointer - AmdAcpiSratPointer DWORD ? - AmdAcpiSratSize DWORD ? - AmdAcpiSlitPointer DWORD ? - AmdAcpiSlitSize DWORD ? - AmdAcpiSsdtPointer DWORD ? - AmdAcpiSsdtSize DWORD ? - AmdAcpiWheaMcePointer DWORD ? - AmdAcpiWheaMceSize DWORD ? - AmdAcpiWheaCmcPointer DWORD ? - AmdAcpiWheaCmcSize DWORD ? - AmdDmiInfoPointer DWORD ? - - ;; Data used for communication between the AP and the BSP. - PUBLIC AmdRunCodeOnApDataPointer - PUBLIC AmdRunCodeOnApDataSize - PUBLIC AmdRunCodeOnApFunction - PUBLIC AmdRunCodeOnApStatus - AmdRunCodeOnApDataPointer DWORD ? - AmdRunCodeOnApDataSize DWORD ? - AmdRunCodeOnApFunction DWORD ? - AmdRunCodeOnApStatus DWORD ? - -CPU_DATASEG_END - - -END diff --git a/src/vendorcode/amd/agesa/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/Legacy/Proc/hobTransfer.c deleted file mode 100644 index d205b5488c..0000000000 --- a/src/vendorcode/amd/agesa/Legacy/Proc/hobTransfer.c +++ /dev/null @@ -1,394 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Hob Transfer functions. - * - * Contains code that copy Heap to temp memory or main memory. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuCacheInit.h" -#include "cpuFamilyTranslation.h" -#include "heapManager.h" -#include "cpuLateInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * CopyHeapToTempRamAtPost - * - * This function copies BSP heap content to RAM - * - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -CopyHeapToTempRamAtPost ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BaseAddressInCache; - UINT8 *BaseAddressInTempMem; - UINT8 *Source; - UINT8 *Destination; - UINT8 AlignTo16ByteInCache; - UINT8 AlignTo16ByteInTempMem; - UINT8 Ignored; - UINT32 SizeOfNodeData; - UINT32 TotalSize; - UINT32 HeapRamFixMtrr; - UINT32 HeapRamVariableMtrr; - UINT32 HeapInCacheOffset; - UINT64 MsrData; - UINT64 VariableMtrrBase; - UINT64 VariableMtrrMask; - UINTN AmdHeapRamAddress; - AGESA_STATUS IgnoredStatus; - BUFFER_NODE *HeapInCache; - BUFFER_NODE *HeapInTempMem; - HEAP_MANAGER *HeapManagerInCache; - HEAP_MANAGER *HeapManagerInTempMem; - CACHE_INFO *CacheInfoPtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - AmdHeapRamAddress = (UINTN) UserOptions.CfgHeapDramAddress; - // - //If the user define address above 1M, Mem Init has already set - //whole available memory as WB cacheable. - // - if (AmdHeapRamAddress < 0x100000) { - // Region below 1MB - // Fixed MTTR region - // turn on modification bit - LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); - MsrData |= 0x80000; - LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); - - if (AmdHeapRamAddress >= 0xC0000) { - // - // 0xC0000 ~ 0xFFFFF - // - HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2)); - MsrData = AMD_MTRR_FIX4K_UC_DRAM; - LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader); - LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader); - } else if (AmdHeapRamAddress >= 0x80000) { - // - // 0x80000~0xBFFFF - // - HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1)); - MsrData = AMD_MTRR_FIX16K_UC_DRAM; - LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader); - } else { - // - // 0x0 ~ 0x7FFFF - // - LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); - MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7)))); - MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7))); - LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); - } - - // Turn on MTTR enable bit and turn off modification bit - LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); - MsrData |= 0x40000; - MsrData &= 0xFFFFFFFFFFF7FFFF; - LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); - } else { - // Region above 1MB - // Variable MTTR region - // Get family specific cache Info - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader); - - // Find an empty MTRRphysBase/MTRRphysMask - for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE; - HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0; - HeapRamVariableMtrr--) { - LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); - LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - if ((VariableMtrrBase == 0) && (VariableMtrrMask == 0)) { - break; - } - } - if (HeapRamVariableMtrr < AMD_MTRR_VARIABLE_BASE0) { - // All variable MTRR is used. - ASSERT (FALSE); - } - - // Set variable MTRR base and mask - // If the address ranges of two or more MTRRs overlap - // and if at least one of the memory types is UC, the UC memory type is used. - VariableMtrrBase = (UINT64) (AmdHeapRamAddress & CacheInfoPtr->HeapBaseMask); - VariableMtrrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK; - LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); - LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - } - // Copying Heap content - if (IsBsp (StdHeader, &IgnoredStatus)) { - TotalSize = sizeof (HEAP_MANAGER); - SizeOfNodeData = 0; - AlignTo16ByteInTempMem = 0; - BaseAddressInCache = (UINT8 *) StdHeader->HeapBasePtr; - HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache; - HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset; - HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); - - BaseAddressInTempMem = (UINT8 *) UserOptions.CfgHeapDramAddress; - HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); - - // copy heap from cache to temp memory. - // only heap with persist great than HEAP_LOCAL_CACHE will be copied. - // Note: Only copy heap with persist greater than HEAP_LOCAL_CACHE. - while (HeapInCacheOffset != AMD_HEAP_INVALID_HEAP_OFFSET) { - if (HeapInCache->Persist > HEAP_LOCAL_CACHE) { - AlignTo16ByteInCache = HeapInCache->PadSize; - AlignTo16ByteInTempMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInTempMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF); - SizeOfNodeData = HeapInCache->BufferSize - AlignTo16ByteInCache; - TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInTempMem); - Source = (UINT8 *) HeapInCache + sizeof (BUFFER_NODE) + AlignTo16ByteInCache; - Destination = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem; - LibAmdMemCopy (HeapInTempMem, HeapInCache, sizeof (BUFFER_NODE), StdHeader); - LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader); - HeapInTempMem->OffsetOfNextNode = TotalSize; - HeapInTempMem->BufferSize = SizeOfNodeData + AlignTo16ByteInTempMem; - HeapInTempMem->PadSize = AlignTo16ByteInTempMem; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); - } - HeapInCacheOffset = HeapInCache->OffsetOfNextNode; - HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); - } - // initialize heap manager - if (TotalSize == sizeof (HEAP_MANAGER)) { - // heap is empty - HeapManagerInTempMem->UsedSize = sizeof (HEAP_MANAGER); - HeapManagerInTempMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapManagerInTempMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); - } else { - // heap is NOT empty - HeapManagerInTempMem->UsedSize = TotalSize; - HeapManagerInTempMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER); - HeapManagerInTempMem->FirstFreeSpaceOffset = TotalSize; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize - SizeOfNodeData - AlignTo16ByteInTempMem - sizeof (BUFFER_NODE)); - HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); - } - // heap signature - HeapManagerInCache->Signature = 0x00000000; - HeapManagerInTempMem->Signature = HEAP_SIGNATURE_VALID; - // Free space node - HeapInTempMem->BufferSize = (UINT32) (AMD_HEAP_SIZE_PER_CORE - TotalSize); - HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - } - return AGESA_SUCCESS; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * CopyHeapToMainRamAtPost - * - * This function copies Temp Ram heap content to Main Ram - * - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -CopyHeapToMainRamAtPost ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BaseAddressInTempMem; - UINT8 *BaseAddressInMainMem; - UINT8 *Source; - UINT8 *Destination; - UINT8 AlignTo16ByteInTempMem; - UINT8 AlignTo16ByteInMainMem; - UINT8 Ignored; - UINT32 SizeOfNodeData; - UINT32 TotalSize; - UINT32 HeapInTempMemOffset; - UINT32 HeapRamVariableMtrr; - UINT64 VariableMtrrBase; - UINT64 VariableMtrrMask; - AGESA_STATUS IgnoredStatus; - BUFFER_NODE *HeapInTempMem; - BUFFER_NODE *HeapInMainMem; - HEAP_MANAGER *HeapManagerInTempMem; - HEAP_MANAGER *HeapManagerInMainMem; - AGESA_BUFFER_PARAMS AgesaBuffer; - CACHE_INFO *CacheInfoPtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - if (IsBsp (StdHeader, &IgnoredStatus)) { - TotalSize = sizeof (HEAP_MANAGER); - SizeOfNodeData = 0; - AlignTo16ByteInMainMem = 0; - BaseAddressInTempMem = (UINT8 *) StdHeader->HeapBasePtr; - HeapManagerInTempMem = (HEAP_MANAGER *) StdHeader->HeapBasePtr; - HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset); - - AgesaBuffer.StdHeader = *StdHeader; - AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE; - AgesaBuffer.BufferLength = AMD_HEAP_SIZE_PER_CORE; - if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - BaseAddressInMainMem = (UINT8 *) AgesaBuffer.BufferPointer; - HeapManagerInMainMem = (HEAP_MANAGER *) BaseAddressInMainMem; - HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize); - LibAmdMemFill (BaseAddressInMainMem, 0x00, AMD_HEAP_SIZE_PER_CORE, StdHeader); - // copy heap from temp memory to main memory. - // only heap with persist great than HEAP_TEMP_MEM will be copied. - // Note: Only copy heap buffers with persist greater than HEAP_TEMP_MEM. - while (HeapInTempMemOffset != AMD_HEAP_INVALID_HEAP_OFFSET) { - if (HeapInTempMem->Persist > HEAP_TEMP_MEM) { - AlignTo16ByteInTempMem = HeapInTempMem->PadSize; - AlignTo16ByteInMainMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInMainMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF); - SizeOfNodeData = HeapInTempMem->BufferSize - AlignTo16ByteInTempMem; - TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInMainMem); - Source = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem; - Destination = (UINT8 *) HeapInMainMem + sizeof (BUFFER_NODE) + AlignTo16ByteInMainMem; - LibAmdMemCopy (HeapInMainMem, HeapInTempMem, sizeof (BUFFER_NODE), StdHeader); - LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader); - HeapInMainMem->OffsetOfNextNode = TotalSize; - HeapInMainMem->BufferSize = SizeOfNodeData + AlignTo16ByteInMainMem; - HeapInMainMem->PadSize = AlignTo16ByteInMainMem; - HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize); - } - HeapInTempMemOffset = HeapInTempMem->OffsetOfNextNode; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset); - } - // initialize heap manager - if (TotalSize == sizeof (HEAP_MANAGER)) { - // heap is empty - HeapManagerInMainMem->UsedSize = sizeof (HEAP_MANAGER); - HeapManagerInMainMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapManagerInMainMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); - } else { - // heap is NOT empty - HeapManagerInMainMem->UsedSize = TotalSize; - HeapManagerInMainMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER); - HeapManagerInMainMem->FirstFreeSpaceOffset = TotalSize; - HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize - SizeOfNodeData - AlignTo16ByteInMainMem - sizeof (BUFFER_NODE)); - HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize); - } - // heap signature - HeapManagerInTempMem->Signature = 0x00000000; - HeapManagerInMainMem->Signature = HEAP_SIGNATURE_VALID; - // Free space node - HeapInMainMem->BufferSize = AMD_HEAP_SIZE_PER_CORE - TotalSize; - HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - } - // if address of heap in temp memory is above 1M, then we must used one variable MTRR. - if (StdHeader->HeapBasePtr >= 0x100000) { - // Find out which variable MTRR was used in CopyHeapToTempRamAtPost. - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader); - for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE; - HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0; - HeapRamVariableMtrr--) { - LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); - LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - if ((VariableMtrrBase == (UINT64) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) && - (VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) { - break; - } - } - if (HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0) { - // Clear variable MTRR which set in CopyHeapToTempRamAtPost. - VariableMtrrBase = 0; - VariableMtrrMask = 0; - LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); - LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - } - } - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/Legacy/agesa.inc b/src/vendorcode/amd/agesa/Legacy/agesa.inc deleted file mode 100644 index 65dd0ef7fa..0000000000 --- a/src/vendorcode/amd/agesa/Legacy/agesa.inc +++ /dev/null @@ -1,2547 +0,0 @@ -; **************************************************************************** -; * -; * @file -; * -; * Agesa structures and definitions -; * -; * Contains AMD AGESA core interface -; * -; * @xrefitem bom "File Content Label" "Release Content" -; * @e project: AGESA -; * @e sub-project: Include -; * @e \$Revision: 41505 $ @e \$Date: 2010-11-05 22:06:20 +0800 (Fri, 05 Nov 2010) $ -; -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** - -INCLUDE amd.inc -UINT64 TEXTEQU <QWORD> -UINT32 TEXTEQU <DWORD> -UINT16 TEXTEQU <WORD> -UINT8 TEXTEQU <BYTE> -CHAR8 TEXTEQU <BYTE> -BOOLEAN TEXTEQU <BYTE> -POINTER TEXTEQU <DWORD> - - ; AGESA Types and Definitions - - - - ; AGESA BASIC CALLOUTS - AGESA_MEM_RELEASE EQU 00028000h - - ; AGESA ADVANCED CALLOUTS, Processor - AGESA_CHECK_UMA EQU 00028100h - AGESA_DO_RESET EQU 00028101h - AGESA_ALLOCATE_BUFFER EQU 00028102h - AGESA_DEALLOCATE_BUFFER EQU 00028103h - AGESA_LOCATE_BUFFER EQU 00028104h - AGESA_RUNFUNC_ONAP EQU 00028105h - - ; AGESA ADVANCED CALLOUTS, HyperTransport - - ; AGESA ADVANCED CALLOUTS, Memory - AGESA_READ_SPD EQU 00028140h - AGESA_HOOKBEFORE_DRAM_INIT EQU 00028141h - AGESA_HOOKBEFORE_DQS_TRAINING EQU 00028142h - AGESA_READ_SPD_RECOVERY EQU 00028143h - AGESA_HOOKBEFORE_EXIT_SELF_REF EQU 00028144h - AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY EQU 00028145h - - ; AGESA IDS CALLOUTS - AGESA_GET_IDS_INIT_DATA EQU 00028200h - - ; AGESA GNB CALLOUTS - AGESA_GNB_PCIE_SLOT_RESET EQU 00028301h -; ------------------------------------------------------------------------ - - ; HyperTransport Interface - - - -; ----------------------------------------------------------------------------- - ; HT DEFINITIONS AND MACROS - -; ----------------------------------------------------------------------------- - - - ; Width equates for call backs - HT_WIDTH_8_BITS EQU 8 - HT_WIDTH_16_BITS EQU 16 - HT_WIDTH_4_BITS EQU 4 - HT_WIDTH_2_BITS EQU 2 - HT_WIDTH_NO_LIMIT EQU HT_WIDTH_16_BITS - - ; Frequency Limit equates for call backs which take a frequency supported mask. - HT_FREQUENCY_LIMIT_200M EQU 1 - HT_FREQUENCY_LIMIT_400M EQU 7 - HT_FREQUENCY_LIMIT_600M EQU 1Fh - HT_FREQUENCY_LIMIT_800M EQU 3Fh - HT_FREQUENCY_LIMIT_1000M EQU 7Fh - HT_FREQUENCY_LIMIT_HT1_ONLY EQU 7Fh - HT_FREQUENCY_LIMIT_1200M EQU 0FFh - HT_FREQUENCY_LIMIT_1400M EQU 1FFh - HT_FREQUENCY_LIMIT_1600M EQU 3FFh - HT_FREQUENCY_LIMIT_1800M EQU 7FFh - HT_FREQUENCY_LIMIT_2000M EQU 0FFFh - HT_FREQUENCY_LIMIT_2200M EQU 1FFFh - HT_FREQUENCY_LIMIT_2400M EQU 3FFFh - HT_FREQUENCY_LIMIT_2600M EQU 7FFFh - HT_FREQUENCY_LIMIT_2800M EQU 27FFFh - HT_FREQUENCY_LIMIT_3000M EQU 67FFFh - HT_FREQUENCY_LIMIT_3200M EQU 0E7FFFh - HT_FREQUENCY_LIMIT_3600M EQU 1E7FFFh - HT_FREQUENCY_LIMIT_MAX EQU HT_FREQUENCY_LIMIT_3600M - HT_FREQUENCY_NO_LIMIT EQU 0FFFFFFFFh - - ; Unit ID Clumping special values - HT_CLUMPING_DISABLE EQU 00000000h - HT_CLUMPING_NO_LIMIT EQU 0FFFFFFFFh - - HT_LIST_TERMINAL EQU 0FFh - HT_LIST_MATCH_ANY EQU 0FEh - HT_LIST_MATCH_INTERNAL_LINK EQU 0FDh - - ; Event Notify definitions - - ; Event definitions. - - ; Coherent subfunction events - HT_EVENT_COH_EVENTS EQU 10001000h - HT_EVENT_COH_NO_TOPOLOGY EQU 10011000h - HT_EVENT_COH_OBSOLETE000 EQU 10021000h - HT_EVENT_COH_PROCESSOR_TYPE_MIX EQU 10031000h - HT_EVENT_COH_NODE_DISCOVERED EQU 10041000h - HT_EVENT_COH_MPCAP_MISMATCH EQU 10051000h - - ; Non-coherent subfunction events - HT_EVENT_NCOH_EVENTS EQU 10002000h - HT_EVENT_NCOH_BUID_EXCEED EQU 10012000h - HT_EVENT_NCOH_OBSOLETE000 EQU 10022000h - HT_EVENT_NCOH_BUS_MAX_EXCEED EQU 10032000h - HT_EVENT_NCOH_CFG_MAP_EXCEED EQU 10042000h - HT_EVENT_NCOH_DEVICE_FAILED EQU 10052000h - HT_EVENT_NCOH_AUTO_DEPTH EQU 10062000h - - ; Optimization subfunction events - HT_EVENT_OPT_EVENTS EQU 10003000h - HT_EVENT_OPT_REQUIRED_CAP_RETRY EQU 10013000h - HT_EVENT_OPT_REQUIRED_CAP_GEN3 EQU 10023000h - HT_EVENT_OPT_UNUSED_LINKS EQU 10033000h - HT_EVENT_OPT_LINK_PAIR_EXCEED EQU 10043000h - - ; HW Fault events - HT_EVENT_HW_EVENTS EQU 10004000h - HT_EVENT_HW_SYNCFLOOD EQU 10014000h - HT_EVENT_HW_HTCRC EQU 10024000h - - ; The Recovery HT component uses 0x10005000 for events. - ; For consistency, we avoid that range here. - - HT_MAX_NC_BUIDS EQU 32 -; ---------------------------------------------------------------------------- - ; HT TYPEDEFS, STRUCTURES, ENUMS - -; ---------------------------------------------------------------------------- -MATCHED EQU 0 ; < The link matches the requested customization. -POWERED_OFF EQU 1 ; < Power the link off. -UNMATCHED EQU 2 ; < The link should be processed according to normal defaults. -MaxFinalLinkState EQU 3 ; < Not a final link state, use for limit checking. -FINAL_LINK_STATE TEXTEQU <DWORD> - - ; Swap a device from its current id to a new one. - -BUID_SWAP_ITEM STRUCT - FromId UINT8 ? ; < The device responding to FromId, - ToId UINT8 ? ; < will be moved to ToId. -BUID_SWAP_ITEM ENDS - - - ; Each Non-coherent chain may have a list of device swaps. After performing the swaps, - ; the final in order list of device ids is provided. (There can be more swaps than devices.) - ; The unused entries in both are filled with 0xFF. - -BUID_SWAP_LIST STRUCT - Swaps BUID_SWAP_ITEM (HT_MAX_NC_BUIDS) DUP ({}) ; < The BUID Swaps to perform - FinalIds UINT8 (HT_MAX_NC_BUIDS) DUP (?) ; < The ordered final BUIDs, resulting from the swaps -BUID_SWAP_LIST ENDS - - - ; Control Manual Initialization of Non-Coherent Chains - - ; This interface is checked every time a non-coherent chain is - ; processed. BUID assignment may be controlled explicitly on a - ; non-coherent chain. Provide a swap list. Swaps controls the - ; BUID assignment and FinalIds provides the device to device - ; Linking. Device orientation can be detected automatically, or - ; explicitly. See interface documentation for more details. - - ; If a manual swap list is not supplied, - ; automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - ; based on each device's unit count. - -MANUAL_BUID_SWAP_LIST STRUCT - ; Match fields - Socket UINT8 ? ; < The Socket on which this chain is located - Link UINT8 ? ; < The Link on the host for this chain - ; Override fields - SwapList BUID_SWAP_LIST {} ; < The swap list -MANUAL_BUID_SWAP_LIST ENDS - - - ; Override options for DEVICE_CAP_OVERRIDE. - - ; Specify which override actions should be performed. For Checks, 1 means to check the item - ; and 0 means to skip the check. For the override options, 1 means to apply the override and - ; 0 means to ignore the override. - -DEVICE_CAP_OVERRIDE_OPTIONS STRUCT - IsCheckDevVenId UINT32 ? -; IN UINT32 IsCheckDevVenId:1; ; < Check Match on Device/Vendor id -; IN UINT32 IsCheckRevision:1; ; < Check Match on device Revision -; IN UINT32 IsOverrideWidthIn:1; ; < Override Width In -; IN UINT32 IsOverrideWidthOut:1; ; < Override Width Out -; IN UINT32 IsOverrideFreq:1; ; < Override Frequency -; IN UINT32 IsOverrideClumping:1; ; < Override Clumping -; IN UINT32 IsDoCallout:1; ; < Make the optional callout -DEVICE_CAP_OVERRIDE_OPTIONS ENDS - - ; Override capabilities of a device. - - ; This interface is checked once for every Link on every IO device. - ; Provide the width and frequency capability if needed for this device. - ; This is used along with device capabilities, the limit interfaces, and northbridge - ; limits to compute the default settings. The components of the device's PCI config - ; address are provided, so its settings can be consulted if need be. - ; The optional callout is a catch all. - -DEVICE_CAP_OVERRIDE STRUCT - ; Match fields - HostSocket UINT8 ? ; < The Socket on which this chain is located. - HostLink UINT8 ? ; < The Link on the host for this chain. - Depth UINT8 ? ; < The Depth in the I/O chain from the Host. - DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00). - Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08). - Link UINT8 ? ; < The Device's Link number (0 or 1). - Options DEVICE_CAP_OVERRIDE_OPTIONS {} ; < The options for this device override. - ; Override fields - LinkWidthIn UINT8 ? ; < modify to change the Link Width In. - LinkWidthOut UINT8 ? ; < modify to change the Link Width Out. - FreqCap UINT32 ? ; < modify to change the Link's frequency capability. - Clumping UINT32 ? ; < modify to change Unit ID clumping support. - Callout CALLOUT_ENTRY ? ; < optional call for really complex cases, or NULL. -DEVICE_CAP_OVERRIDE ENDS - - ; Callout param struct for override capabilities of a device. - - ; If the optional callout is implemented this param struct is passed to it. - -DEVICE_CAP_CALLOUT_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < The header - ; Match fields - HostSocket UINT8 ? ; < The Socket on which this chain is located. - HostLink UINT8 ? ; < The Link on the host for this chain. - Depth UINT8 ? ; < The Depth in the I/O chain from the Host. - DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00). - Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08). - Link UINT8 ? ; < The Device's Link number (0 or 1). - PciAddress PCI_ADDR {} ; < The Device's PCI Address. - ; Override fields - LinkWidthIn POINTER ? ; < modify to change the Link Width In. - LinkWidthOut POINTER ? ; < modify to change the Link Width Out. - FreqCap POINTER ? ; < modify to change the Link's frequency capability. - Clumping POINTER ? ; < modify to change Unit ID clumping support. -DEVICE_CAP_CALLOUT_PARAMS ENDS - - ; Limits for CPU to CPU Links. - - ; For each coherent connection this interface is checked once. - ; Provide the frequency and width if needed for this Link (usually based on board - ; restriction). This is used with CPU device capabilities and northbridge limits - ; to compute the default settings. - -CPU_TO_CPU_PCB_LIMITS STRUCT - ; Match fields - SocketA UINT8 ? ; < One Socket on which this Link is located - LinkA UINT8 ? ; < The Link on this Node - SocketB UINT8 ? ; < The other Socket on which this Link is located - LinkB UINT8 ? ; < The Link on that Node - ; Limit fields - ABLinkWidthLimit UINT8 ? ; < modify to change the Link Width A->B - BALinkWidthLimit UINT8 ? ; < modify to change the Link Width B-<A - PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability -CPU_TO_CPU_PCB_LIMITS ENDS - - ; Get limits for non-coherent Links. - - ; For each non-coherent connection this interface is checked once. - ; Provide the frequency and width if needed for this Link (usually based on board - ; restriction). This is used with device capabilities, device overrides, and northbridge limits - ; to compute the default settings. - -IO_PCB_LIMITS STRUCT - ; Match fields - HostSocket UINT8 ? ; < The Socket on which this Link is located - HostLink UINT8 ? ; < The Link about to be initialized - Depth UINT8 ? ; < The Depth in the I/O chain from the Host - ; Limit fields - DownstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width going away from processor - UpstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width moving toward processor - PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability -IO_PCB_LIMITS ENDS - - ; Manually control bus number assignment. - - ; This interface is checked every time a non-coherent chain is processed. - ; If a system can not use the auto Bus numbering feature for non-coherent chain bus - ; assignments, this interface can provide explicit control. For each chain, provide - ; the bus number range to use. - -OVERRIDE_BUS_NUMBERS STRUCT - ; Match fields - Socket UINT8 ? ; < The Socket on which this chain is located - Link UINT8 ? ; < The Link on the host for this chain - ; Override fields - SecBus UINT8 ? ; < Secondary Bus number for this non-coherent chain - SubBus UINT8 ? ; < Subordinate Bus number -OVERRIDE_BUS_NUMBERS ENDS - - - ; Ignore a Link. - - ; This interface is checked every time a coherent Link is found and then every - ; time a non-coherent Link from a CPU is found. - ; Any coherent or non-coherent Link from a CPU can be ignored and not used - ; for discovery or initialization. Useful for connection based systems. - ; (Note: not checked for IO device to IO Device Links.) - -IGNORE_LINK STRUCT - ; Match fields - Socket UINT8 ? ; < The Socket on which this Link is located - Link UINT8 ? ; < The Link about to be initialized - ; Customization fields - LinkState FINAL_LINK_STATE ? ; < The link may be left unitialized, or powered off. -IGNORE_LINK ENDS - - - ; Skip reganging of subLinks. - - ; This interface is checked whenever two subLinks are both connected to the same CPUs. - ; Normally, unganged sublinks between the same two CPUs are reganged. - ; Provide a matching structure to leave the Links unganged. - -SKIP_REGANG STRUCT - ; Match fields - SocketA UINT8 ? ; < One Socket on which this Link is located - LinkA UINT8 ? ; < The Link on this Node - SocketB UINT8 ? ; < The other Socket on which this Link is located - LinkB UINT8 ? ; < The Link on that Node - ; Customization fields - LinkState FINAL_LINK_STATE ? ; < The paired sublink may be active, or powered off. -SKIP_REGANG ENDS - - ; The System Socket layout, which sockets are physically connected. - - ; The hardware method for Socket naming is preferred. Use this software method only - ; if required. - -SYSTEM_PHYSICAL_SOCKET_MAP STRUCT - CurrentSocket UINT8 ? ; < The socket from which this connection originates. - CurrentLink UINT8 ? ; < The Link from the source socket connects to another socket. - TargetSocket UINT8 ? ; < The target socket which is connected on that link. -SYSTEM_PHYSICAL_SOCKET_MAP ENDS - -; ---------------------------------------------------------------------------- - - ; This is the input structure for AmdHtInitialize. - -AMD_HT_INTERFACE STRUCT - ; Basic level customization - AutoBusStart UINT8 ? ; < For automatic bus number assignment, starting bus number usually zero. - AutoBusMax UINT8 ? ; < For automatic bus number assignment, do not assign above max. - AutoBusIncrement UINT8 ? ; < For automatic bus number assignment, each chain gets this many busses. - - ; Advanced Level Customization - ManualBuidSwapList POINTER ? ; < Provide Manual Swap List, if any. - DeviceCapOverrideList POINTER ? ; < Provide Device Overrides, if any. - CpuToCpuPcbLimitsList POINTER ? ; < Provide CPU PCB Limits, if any. - IoPcbLimitsList POINTER ? ; < Provide IO PCB Limits, if any. - OverrideBusNumbersList POINTER ? ; < Provide manual Bus Number assignment, if any. - ; < Use either auto bus numbering or override bus - ; < numbers, not both. - - IgnoreLinkList POINTER ? ; < Provide links to ignore, if any. - SkipRegangList POINTER ? ; < Provide links to remain unganged, if any. - - ; Expert Level Customization - Topolist POINTER ? ; < Use this topology list in addition to the built in, if not NULL. - SystemPhysicalSocketMap POINTER ? - ; < The hardware socket naming method is preferred, - ; < If it can't be used, this provides a software method. -AMD_HT_INTERFACE ENDS - -; ----------------------------------------------------------------------------- - - ; HT Recovery Interface - - - -; ----------------------------------------------------------------------------- -; * HT Recovery DEFINITIONS AND MACROS -; * -; *----------------------------------------------------------------------------- -; - - ; BBHT subfunction events - HT_EVENT_BB_EVENTS EQU 10005000h - HT_EVENT_BB_BUID_EXCEED EQU 10015000h - HT_EVENT_BB_DEVICE_FAILED EQU 10055000h - HT_EVENT_BB_AUTO_DEPTH EQU 10065000h - -; ---------------------------------------------------------------------------- -; * HT Recovery TYPEDEFS, STRUCTURES, ENUMS -; * -; *---------------------------------------------------------------------------- -; - - - ; The Interface structure to Recovery HT. - -AMD_HT_RESET_INTERFACE STRUCT - ManualBuidSwapList POINTER ? ; < Option to manually control SB link init - Depth UINT32 ? ; < If auto init was used this is set to the depth of the chain, - ; < else, for manual init unmodified. -AMD_HT_RESET_INTERFACE ENDS - -; --------------------------------------------------------------------------- -; CPU Feature related info -; --------------------------------------------------------------------------- - ; Build Configuration values for BLDCFG_PLATFORM_C1E_MODE - C1eModeDisabled EQU 0 ; < Disabled - C1eModeHardware EQU 1 ; < Hardware method - C1eModeMsgBased EQU 2 ; < Message-based method - C1eModeSoftwareDeprecated EQU 3 ; < Deprecated software SMI method - C1eModeHardwareSoftwareDeprecated EQU 4 ; < Hardware or Deprecated software SMI method - MaxC1eMode EQU 5 ; < Not a valid value, used for verifying input -PLATFORM_C1E_MODES TEXTEQU <DWORD> - - ; Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE - CStateModeDisabled EQU 0 ; < Disabled - CStateModeC6 EQU 1 ; < C6 State - MaxCStateMode EQU 2 ; < Not a valid value, used for verifying input -PLATFORM_CSTATE_MODES TEXTEQU <DWORD> - - ; Build Configuration values for BLDCFG_PLATFORM_CPB_MODE - CpbModeAuto EQU 0 ; < Auto - CpbModeDisabled EQU 1 ; < Disabled - MaxCpbMode EQU 2 ; < Not a valid value, used for verifying input -PLATFORM_CPB_MODES TEXTEQU <DWORD> - - -;---------------------------------------------------------------------------- -; GNB PCIe configuration info -;---------------------------------------------------------------------------- - -GNB_EVENT_INVALID_CONFIGURATION EQU 20010000h ; User configuration invalid -GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION EQU 20010001h ; Requested lane allocation for PCIe port can not be supported -GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION EQU 20010002h ; Requested incorrect PCIe port device address -GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION EQU 20010003h ; Incorrect parameter in DDI link configuration -GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION EQU 20010004h ; Invalid with for PCIe port or DDI link -GNB_EVENT_INVALID_LANES_CONFIGURATION EQU 20010005h ; Lane double subscribe lanes -GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION EQU 20010006h ; Requested lane allocation for DDI link(s) can not be supported -GNB_EVENT_LINK_TRAINING_FAIL EQU 20020000h ; PCIe Link training fail -GNB_EVENT_BROKEN_LANE_RECOVERY EQU 20030000h ; Broken lane workaround applied to recover link training -GNB_EVENT_GEN2_SUPPORT_RECOVERY EQU 20040000h ; Scale back to GEN1 to recover link training - -DESCRIPTOR_TERMINATE_LIST EQU 80000000h - -PCIe_PORT_MISC_CONTROL STRUCT - LinkComplianceMode UINT8 ? - ;IN UINT8 LinkComplianceMode :1; ;< Force port into compliance mode (device will not be trained, port output compliance pattern) -PCIe_PORT_MISC_CONTROL ENDS - -PCIe_PORT_DATA STRUCT - PortPresent UINT8 ? ; < Enable PCIe port for initialization. - ChannelType UINT8 ? ; < Channel type. - ; 0 - "lowLoss", - ; 1 - "highLoss", - ; 2 - "mob0db", - ; 3 - "mob3db", - ; 4 - "extnd6db" - ; 5 - "extnd8db" - ; - DeviceNumber UINT8 ? ; < Device number for port. Available device numbers may very on different CPUs. - FunctionNumber UINT8 ? ; < Reserved for future use - LinkSpeedCapability UINT8 ? ; < Advertised Gen Capability - ; 0 - Maximum supported by silicon - ; 1 - Gen1 - ; 2 - Gen2 - ; 3 - Gen3 - ; - LinkAspm UINT8 ? ; < ASPM control. (see OemPcieLinkAspm for additional option to control ASPM) - ; 0 - Disabled - ; 1 - L0s only - ; 2 - L1 only - ; 2 - L0s and L1 - ; - LinkHotplug UINT8 ? ; < Hotplug control. - ; 0 - Disabled - ; 1 - Basic - ; 2 - Server - ; 3 - Enhanced - ; - ResetId UINT8 ? ; < Arbitrary number greater than 0 assigned by platform firmware for GPIO - ; identification which control reset for given port. - ; Each port with unique GPIO should have unique ResetId assigned. - ; All ports use same GPIO to control reset should have same ResetId assigned. - ; see AgesaPcieSlotResetControl - ; - MiscControls PCIe_PORT_MISC_CONTROL {} ; < Misc extended controls -PCIe_PORT_DATA ENDS - -;DDI channel lane mapping - -CHANNEL_MAPPING STRUCT ; - Lane0 UINT8 ? ; - ;IN UINT8 Lane0 :2; ; - ;IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping") - ;IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping") - ;IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping") -CHANNEL_MAPPING ENDS ; - -CONN_CHANNEL_MAPPING UNION - ChannelMappingValue UINT8 ? ; < Raw lane mapping - ChannelMapping CHANNEL_MAPPING {} ; -CONN_CHANNEL_MAPPING ENDS ; - -; DDI Configuration -PCIe_DDI_DATA STRUCT - ConnectorType UINT8 ? ; < Display Connector Type - ; 0 - DP - ; 1 - eDP - ; 2 - Single Link DVI - ; 3 - Dual Link DVI - ; 4 - HDMI - ; 5 - Travis DP-to-VGA - ; 6 - Travis DP-to-LVDS - ; 7 - Hudson-2 NutMeg DP-to-VGA - ; 8 - Single Link DVI-I - ; 9 - CRT (VGA) - ; 10 - LVDS - ; 11 - VBIOS auto detect connector type - AuxIndex UINT8 ? ; < Indicates which AUX or DDC Line is used - ; 0 - AUX1 - ; 1 - AUX2 - ; 2 - AUX3 - ; 3 - AUX4 - ; 4 - AUX5 - ; 5 - AUX6 - ; - HdpIndex UINT8 ? ; < Indicates which HDP pin is used - ; 0 - HDP1 - ; 1 - HDP2 - ; 2 - HDP3 - ; 3 - HDP4 - ; 4 - HDP5 - ; 5 - HDP6 - Mapping CONN_CHANNEL_MAPPING (2) DUP ({}) ;< Set specific mapping of lanes to connector pins - ;Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane - ;Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only - ;applicable for Dual DDI link) - ;if Mapping[x] set to 0 than default mapping assumed - -PCIe_DDI_DATA ENDS - - -; Engine Configuration -PCIe_ENGINE_DATA STRUCT - EngineType UINT8 ? ; < Engine type - ; 0 - Ignore engine configuration - ; 1 - PCIe port - ; 2 - DDI - StartLane UINT16 ? ; < Start lane number (in reversed configuration StartLane > EndLane). - EndLane UINT16 ? ; < End lane number (in reversed configuration StartLane > EndLane). -PCIe_ENGINE_DATA ENDS - -; PCIe port descriptor -PCIe_PORT_DESCRIPTOR STRUCT - Flags UINT32 ? ; < Descriptor flags - ; Bit31 - last descriptor in complex - EngineData PCIe_ENGINE_DATA {} ; < Engine data - Port PCIe_PORT_DATA {} ; < PCIe port specific configuration info -PCIe_PORT_DESCRIPTOR ENDS - -; DDI descriptor -PCIe_DDI_DESCRIPTOR STRUCT - Flags UINT32 ? ; < Descriptor flags - EngineData PCIe_ENGINE_DATA {} ; < Engine data - Ddi PCIe_DDI_DATA {} ; < DDI port specific configuration info -PCIe_DDI_DESCRIPTOR ENDS - -; Slot Reset Info -PCIe_SLOT_RESET_INFO STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header - ResetId UINT8 ? ; < Slot reset ID as specified in PCIe_PORT_DESCRIPTOR - ResetControl UINT8 ? ; < Reset control as defined by PCIE_RESET_CONTROL -PCIe_SLOT_RESET_INFO ENDS - - -; PCIe Complex descriptor -PCIe_COMPLEX_DESCRIPTOR STRUCT - Flags UINT32 ? ; < Descriptor flags - ; Bit31 - last descriptor in topology - ; - ; - SocketId UINT32 ? ; < Socket Id - PciePortList POINTER ? ;< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). - DdiLinkList POINTER ? ;< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). - Reserved POINTER ? ;< Reserved for future use -PCIe_COMPLEX_DESCRIPTOR ENDS - - AssertSlotReset EQU 0 - DeassertSlotReset EQU 1 -PCIE_RESET_CONTROL TEXTEQU <DWORD> - - PcieUnusedEngine EQU 0 - PciePortEngine EQU 1 - PcieDdiEngine EQU 2 - MaxPcieEngine EQU 3 ; < Not a valid value, used for verifying input -PCIE_ENGINE_TYPE TEXTEQU <DWORD> - - PcieGenMaxSupported EQU 0 - PcieGen1 EQU 1 - PcieGen2 EQU 2 - MaxPcieGen EQU 3 ; < Not a valid value, used for verifying input -PCIE_LINK_SPEED_CAP TEXTEQU <DWORD> - - PsppDisabled EQU 0 - PsppPerformance EQU 1 - PsppBalanceHigh EQU 2 - PsppBalanceLow EQU 3 - PsppPowerSaving EQU 4 - MaxPspp EQU 5 ; < Not a valid value, used for verifying input -PCIE_PSPP_POLICY TEXTEQU <DWORD> - - ConnectorTypeDP EQU 0 - ConnectorTypeEDP EQU 1 - ConnectorTypeSingleLinkDVI EQU 2 - ConnectorTypeDualLinkDVI EQU 3 - ConnectorTypeHDMI EQU 4 - ConnectorTypeTravisDpToVga EQU 5 - ConnectorTypeTravisDpToLvds EQU 6 - ConnectorTypeNutmegDpToVga EQU 7 - ConnectorTypeSingleLinkDviI EQU 8 - ConnectorTypeCrt EQU 9 - ConnectorTypeLvds EQU 10 - ConnectorTypeAutoDetect EQU 11 - MaxConnectorType EQU 12 ; < Not a valid value, used for verifying input -PCIE_CONNECTOR_TYPE TEXTEQU <DWORD> - - ChannelTypeLowLoss EQU 0 - ChannelTypeHighLoss EQU 1 - ChannelTypeMob0db EQU 2 - ChannelTypeMob3db EQU 3 - ChannelTypeExt6db EQU 4 - ChannelTypeExt8db EQU 5 - MaxChannelType EQU 6 ; < Not a valid value, used for verifying input -PCIE_CHANNEL_TYPE TEXTEQU <DWORD> - - AspmDisabled EQU 0 - AspmL0s EQU 1 - AspmL1 EQU 2 - AspmL0sL1 EQU 3 - MaxAspm EQU 4 ; < Not a valid value, used for verifying input -PCIE_ASPM_TYPE TEXTEQU <DWORD> - - HotplugDisabled EQU 0 - HotplugBasic EQU 1 - HotplugServer EQU 2 - HotplugEnhanced EQU 3 - HotplugInboard EQU 4 - MaxHotplug EQU 5 ; < Not a valid value, used for verifying input -PCIE_HOTPLUG_TYPE TEXTEQU <DWORD> - - PortDisabled EQU 0 - PortEnabled EQU 1 -PCIE_PORT_ENABLE TEXTEQU <DWORD> - - Aux1 EQU 0 - Aux2 EQU 1 - Aux3 EQU 2 - Aux4 EQU 3 - Aux5 EQU 4 - Aux6 EQU 5 - MaxAux EQU 6 ; < Not a valid value, used for verifying input -PCIE_AUX_TYPE TEXTEQU <DWORD> - - Hdp1 EQU 0 - Hdp2 EQU 1 - Hdp3 EQU 2 - Hdp4 EQU 3 - Hdp5 EQU 4 - Hdp6 EQU 5 - MaxHdp EQU 6 ; < Not a valid value, used for verifying input -PCIE_HDP_TYPE TEXTEQU <DWORD> - -;---------------------------------------------------------------------------- -; GNB configuration info -;---------------------------------------------------------------------------- -; - -; Configuration settings for GNB. -GNB_ENV_CONFIGURATION STRUCT - Gnb3dStereoPinIndex UINT8 ? ;< 3D Stereo Pin ID. - ; @li 0 = Stereo 3D is disabled (default). - ; @li 1 = Use processor pin HPD1. - ; @li 2 = Use processor pin HPD2 - ; @li 3 = Use processor pin HPD3 - ; @li 4 = Use processor pin HPD4 - ; @li 5 = Use processor pin HPD5 - ; @li 6 = Use processor pin HPD6 - LvdsSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 % - LvdsSpreadSpectrumRate UINT16 ? ; Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz -GNB_ENV_CONFIGURATION ENDS - -; GNB configuration info -GNB_CONFIGURATION STRUCT - PcieComplexList POINTER ? ; Pointer to array of PCIe_COMPLEX_DESCRIPTOR structures describe PCIe topology on each processor package or NULL. - ; Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST - ; - ; - ; - ; Topology organization definition assume PCIe_COMPLEX_DESCRIPTOR defined first following - ; PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR for given PCIe_COMPLEX_DESCRIPTOR - ; defined in arbitrary sequence: - ; Example of topology definition for single socket system: - ; PlatfromTopology LABEL DWORD - ; - ; Port0_2 PCIe_PORT_DESCRIPTOR <>; - ; Port0_3 PCIe_PORT_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST> ; - ; ... - ; Ddi0_A PCIe_DDI_DESCRIPTOR <>; - ; Ddi0_B PCIe_DDI_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST,>; - ; ... - ; Cpu0 PCIe_COMPLEX_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST, 0, Port0_2, Ddi0_A> - ; - ; - PsppPolicy UINT8 ? ;< PSPP (PCIe Speed Power Policy) - ; @li @b 0 - Disabled - ; @li @b 1 - Performance - ; @li @b 2 - Balance-High - ; @li @b 3 - Balance-Low - ; @li @b 4 - Power Saving - ; -GNB_CONFIGURATION ENDS - - -; --------------------------------------------------------------------------- - -; MEMORY-SPECIFIC DATA STRUCTURES - -; --------------------------------------------------------------------------- - - - ; AGESA MAXIMIUM VALUES - - ; These Max values are used to define array sizes and associated loop - ; counts in the code. They reflect the maximum values that AGESA - ; currently supports and does not necessarily reflect the hardware - ; capabilities of configuration. - - - MAX_SOCKETS_SUPPORTED EQU 8 ; < Max number of sockets in system - MAX_CHANNELS_PER_SOCKET EQU 4 ; < Max Channels per sockets - MAX_DIMMS_PER_CHANNEL EQU 4 ; < Max DIMMs on a memory channel (independent of platform) - NUMBER_OF_DELAY_TABLES EQU 9 ; < Number of tables defined in CH_DEF_STRUCT. - ; < Eg: UINT16 *RcvEnDlys; - ; < UINT8 *WrDqsDlys; - ; < UINT8 *RdDqsDlys; - ; < UINT8 *WrDatDlys; - ; < UINT8 *RdDqsMinDlys; - ; < UINT8 *RdDqsMaxDlys; - ; < UINT8 *WrDatMinDlys; - ; < UINT8 *WrDatMaxDlys; - NUMBER_OF_FAILURE_MASK_TABLES EQU 1 ; < Number of failure mask tables - MAX_PLATFORM_TYPES EQU 16 ; < Platform types per system - - MCT_TRNG_KEEPOUT_START EQU 00004000h ; < base [39:8] - MCT_TRNG_KEEPOUT_END EQU 00007FFFh ; < base [39:8] - - UMA_ATTRIBUTE_INTERLEAVE EQU 80000000h ; < Uma Region is interleaved - UMA_ATTRIBUTE_ON_DCT0 EQU 40000000h ; < UMA resides on memory that belongs to DCT0 - UMA_ATTRIBUTE_ON_DCT1 EQU 20000000h ; < UMA resides on memory that belongs to DCT1 - - PSO_TABLE TEXTEQU <UINT8>; < Platform Configuration Table - - ; AGESA DEFINITIONS - - ; Many of these are derived from the platform and hardware specific definitions - - ; EccSymbolSize override value - ECCSYMBOLSIZE_USE_BKDG EQU 0 ; < Use BKDG Recommended Value - ECCSYMBOLSIZE_FORCE_X4 EQU 4 ; < Force to x4 - ECCSYMBOLSIZE_FORCE_X8 EQU 8 ; < Force to x8 - ; CPU Package Type - PT_L1 EQU 0 ; < L1 Package type - PT_M2 EQU 1 ; < AM Package type - PT_S1 EQU 2 ; < S1 Package type - - ; Structures use to pass system Logical CPU-ID -CPU_LOGICAL_ID STRUCT - Family UINT64 ? ; < Indicates logical ID Family - Revision UINT64 ? ; < Indicates logical ID Family -CPU_LOGICAL_ID ENDS - - ; Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE - - AMD_PLATFORM_SERVER EQU 8000h ; < Server - AMD_PLATFORM_DESKTOP EQU 10000h ; < Desktop - AMD_PLATFORM_MOBILE EQU 20000h ; < Mobile -AMD_PLATFORM_TYPE TEXTEQU <DWORD> - - ; Dram technology type - - DDR2_TECHNOLOGY EQU 0 ; < DDR2 technology - DDR3_TECHNOLOGY EQU 1 ; < DDR3 technology -TECHNOLOGY_TYPE TEXTEQU <DWORD> - - ; Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT - - DDR400_FREQUENCY EQU 200 ; < DDR 400 - DDR533_FREQUENCY EQU 266 ; < DDR 533 - DDR667_FREQUENCY EQU 333 ; < DDR 667 - DDR800_FREQUENCY EQU 400 ; < DDR 800 - DDR1066_FREQUENCY EQU 533 ; < DDR 1066 - DDR1333_FREQUENCY EQU 667 ; < DDR 1333 - DDR1600_FREQUENCY EQU 800 ; < DDR 1600 - DDR1866_FREQUENCY EQU 933 ; < DDR 1866 - UNSUPPORTED_DDR_FREQUENCY EQU 934 ; < Highest limit of DDR frequency -MEMORY_BUS_SPEED TEXTEQU <DWORD> - - ; Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE - - QUADRANK_REGISTERED EQU 0 - QUADRANK_UNBUFFERED EQU 1 -QUANDRANK_TYPE TEXTEQU <DWORD> - - ; Build Configuration values for BLDCFG_TIMING_MODE_SELECT - - TIMING_MODE_AUTO EQU 0 ; < Use best rate possible - TIMING_MODE_LIMITED EQU 1 ; < Set user top limit - TIMING_MODE_SPECIFIC EQU 2 ; < Set user specified speed -USER_MEMORY_TIMING_MODE TEXTEQU <DWORD> - - ; Build Configuration values for BLDCFG_POWER_DOWN_MODE - - POWER_DOWN_BY_CHANNEL EQU 0 - POWER_DOWN_BY_CHIP_SELECT EQU 1 - POWER_DOWN_AUTO EQU 2 -POWER_DOWN_MODE TEXTEQU <DWORD> - - ; Low voltage support - - VOLT1_5 EQU 0 ; < 1.5 Volt - VOLT1_35 EQU 1 ; < 1.35 Volt - VOLT1_25 EQU 2 ; < 1.25 Volt - VOLT_UNSUPPORTED EQU 0xFF ; < No common voltage found -DIMM_VOLTAGE TEXTEQU <DWORD> - - ; UMA Mode - - UMA_NONE EQU 0 ; < UMA None - UMA_SPECIFIED EQU 1 ; < UMA Specified - UMA_AUTO EQU 2 ; < UMA Auto -UMA_MODE TEXTEQU <DWORD> - - ; Build Configuration values for BLDCFG_UMA_ALIGNMENT - - NO_UMA_ALIGNED EQU 00FFFFFFh - UMA_128MB_ALIGNED EQU 00FFF800h - UMA_256MB_ALIGNED EQU 00FFF000h - UMA_512MB_ALIGNED EQU 00FFE000h -UMA_ALIGNMENT TEXTEQU <DWORD> - ; =============================================================================== - ; Global MCT Configuration Status Word (GStatus) - ; =============================================================================== - - GsbMTRRshort EQU 0 ; < Ran out of MTRRs while mapping memory - GsbAllECCDimms EQU 1 ; < All banks of all Nodes are ECC capable - GsbDramECCDis EQU 2 ; < Dram ECC requested but not enabled. - GsbSoftHole EQU 3 ; < A Node Base gap was created - GsbHWHole EQU 4 ; < A HW dram remap was created - GsbNodeIntlv EQU 5 ; < Node Memory interleaving was enabled - GsbSpIntRemapHole EQU 6 ; < Special condition for Node Interleave and HW remapping - GsbEnDIMMSpareNW EQU 7 ; < Indicates that DIMM Spare can be used without a warm reset - - GsbEOL EQU 8 ; < End of list -GLOBAL_STATUS_FIELD TEXTEQU <DWORD> - -; =============================================================================== - ; Local Error Status (DIE_STRUCT.ErrStatus[31:0]) -; =============================================================================== - - EsbNoDimms EQU 0 ; < No DIMMs - EsbSpdChkSum EQU 1 ; < SPD Checksum fail - EsbDimmMismatchM EQU 2 ; < dimm module type(buffer) mismatch - EsbDimmMismatchT EQU 3 ; < dimm CL/T mismatch - EsbDimmMismatchO EQU 4 ; < dimm organization mismatch (128-bit) - EsbNoTrcTrfc EQU 5 ; < SPD missing Trc or Trfc info - EsbNoCycTime EQU 6 ; < SPD missing byte 23 or 25 - EsbBkIntDis EQU 7 ; < Bank interleave requested but not enabled - EsbDramECCDis EQU 8 ; < Dram ECC requested but not enabled - EsbSpareDis EQU 9 ; < Online spare requested but not enabled - EsbMinimumMode EQU 10 ; < Running in Minimum Mode - EsbNoRcvrEn EQU 11 ; < No DQS Receiver Enable pass window found - EsbSmallRcvr EQU 12 ; < DQS Rcvr En pass window too small (far right of dynamic range) - EsbNoDqsPos EQU 13 ; < No DQS-DQ passing positions - EsbSmallDqs EQU 14 ; < DQS-DQ passing window too small - EsbDCBKScrubDis EQU 15 ; < DCache scrub requested but not enabled - - EsbEMPNotSupported EQU 16 ; < Processor is not capable for EMP. - EsbEMPConflict EQU 17 ; < EMP requested but cannot be enabled since - ; < channel interleaving, bank interleaving, or bank swizzle is enabled. - EsbEMPDis EQU 18 ; < EMP requested but cannot be enabled since - ; < memory size of each DCT is not a power of two. - - EsbEOL EQU 19 ; < End of list -ERROR_STATUS_FIELD TEXTEQU <DWORD> - -; =============================================================================== - ; Local Configuration Status (DIE_STRUCT.Status[31:0]) -; =============================================================================== - - SbRegistered EQU 0 ; < All DIMMs are Registered - SbEccDimms EQU 1 ; < All banks ECC capable - SbParDimms EQU 2 ; < All banks Addr/CMD Parity capable - SbDiagClks EQU 3 ; < Jedec ALL slots clock enable diag mode - Sb128bitmode EQU 4 ; < DCT in 128-bit mode operation - Sb64MuxedMode EQU 5 ; < DCT in 64-bit mux'ed mode. - Sb2TMode EQU 6 ; < 2T CMD timing mode is enabled. - SbSWNodeHole EQU 7 ; < Remapping of Node Base on this Node to create a gap. - SbHWHole EQU 8 ; < Memory Hole created on this Node using HW remapping. - SbOver400Mhz EQU 9 ; < DCT freq greater than or equal to 400MHz flag - SbDQSPosPass2 EQU 10 ; < Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz - SbDQSRcvLimit EQU 11 ; < Used for DQSRcvEnTrain to know we have reached the upper bound. - SbExtConfig EQU 12 ; < Indicate the default setting for extended PCI configuration support - SbLrdimms EQU 13 ; < All DIMMs are LRDIMMs - SbEOL EQU 14 ; < End of list -LOCAL_STATUS_FIELD TEXTEQU <DWORD> - - -; < CPU MSR Register definitions ------------------------------------------ - SYS_CFG EQU 0C0010010h - TOP_MEM EQU 0C001001Ah - TOP_MEM2 EQU 0C001001Dh - HWCR EQU 0C0010015h - NB_CFG EQU 0C001001Fh - - FS_BASE EQU 0C0000100h - IORR0_BASE EQU 0C0010016h - IORR0_MASK EQU 0C0010017h - BU_CFG EQU 0C0011023h - BU_CFG2 EQU 0C001102Ah - COFVID_STAT EQU 0C0010071h - TSC EQU 10h - -; =============================================================================== - ; SPD Data for each DIMM -; =============================================================================== -SPD_DEF_STRUCT STRUCT - DimmPresent BOOLEAN ? ; < Indicates that the DIMM is present and Data is valid - Data UINT8 (256) DUP (?) ; < Buffer for 256 Bytes of SPD data from DIMM -SPD_DEF_STRUCT ENDS - -; =============================================================================== - ; Channel Definition Structure - ; This data structure defines entries that are specific to the channel initialization -; =============================================================================== -CH_DEF_STRUCT STRUCT - ChannelID UINT8 ? ; < Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D) - TechType TECHNOLOGY_TYPE ? ; < Technology type of this channel - ChDimmPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is present. - ; < DIMM# Select Signal - ; < 0 MA0_CS_L[0, 1] - ; < 1 MB0_CS_L[0, 1] - ; < 2 MA1_CS_L[0, 1] - ; < 3 MB1_CS_L[0, 1] - ; < 4 MA2_CS_L[0, 1] - ; < 5 MB2_CS_L[0, 1] - ; < 6 MA3_CS_L[0, 1] - ; < 7 MB3_CS_L[0, 1] - - DCTPtr POINTER ? ; < Pointer to the DCT data of this channel. - MCTPtr POINTER ? ; < Pointer to the node data of this channel. - SpdPtr POINTER ? ; < Pointer to the SPD data for this channel. (Setup by NB Constructor) - DimmSpdPtr POINTER (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of pointers to - ; < SPD Data for each Dimm. (Setup by Tech Block Constructor) - ChDimmValid UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved. - RegDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved. - LrDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved. - SODimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a SO-DIMM where 4..7 are reserved. - Loads UINT8 ? ; < Number of devices loading bus - Dimms UINT8 ? ; < Number of DIMMs loading Channel - Ranks UINT8 ? ; < Number of ranks loading Channel DATA - SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode) - ; < FALSE = 1T - ; < TRUE = 2T - ; < The following pointers will be pointed to dynamically allocated buffers. - ; < Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below. - ; < Example: If DIMM and Byte based training, then - ; < XX is a value in Hex - ; < BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE - ; < Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX - ; < Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX - RcvEnDlys POINTER ? ; < DQS Receiver Enable Delays - WrDqsDlys POINTER ? ; < Write DQS delays (only valid for DDR3) - RdDqsDlys POINTER ? ; < Read Dqs delays - WrDatDlys POINTER ? ; < Write Data delays - RdDqsMinDlys POINTER ? ; < Minimum Window for Read DQS - RdDqsMaxDlys POINTER ? ; < Maximum Window for Read DQS - WrDatMinDlys POINTER ? ; < Minimum Window for Write data - WrDatMaxDlys POINTER ? ; < Maximum Window for Write data - RowCount UINT8 ? ; < Number of rows of the allocated buffer. - ColumnCount UINT8 ? ; < Number of columns of the allocated buffer. - - FailingBitMask POINTER ? ; < Table of masks to Track Failing bits - DctOdcCtl UINT32 ? ; < Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h) - DctAddrTmg UINT32 ? ; < Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h) - PhyRODTCSLow UINT32 ? ; < Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h) - PhyRODTCSHigh UINT32 ? ; < Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h) - PhyWODTCSLow UINT32 ? ; < Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h) - PhyWODTCSHigh UINT32 ? ; < Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183) - PhyWLODT UINT8 (4) DUP (?) ; < Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8]) - DctEccDqsLike UINT16 ? ; < DCT DQS ECC UINT8 like... - DctEccDqsScale UINT8 ? ; < DCT DQS ECC UINT8 scale - PtrPatternBufA UINT16 ? ; < Ptr on stack to aligned DQS testing pattern - PtrPatternBufB UINT16 ? ; < Ptr on stack to aligned DQS testing pattern - ByteLane UINT8 ? ; < Current UINT8 Lane (0..7) - Direction UINT8 ? ; < Current DQS-DQ training write direction (0=read, 1=write) - Pattern UINT8 ? ; < Current pattern - DqsDelay UINT8 ? ; < Current DQS delay value - HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space. - HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space. - DctMaxRdLat UINT16 ? ; < Max Read Latency (ns) for the DCT - DIMMValidCh UINT8 ? ; < DIMM# in CH - MaxCh UINT8 ? ; < Max number of CH in system - Dct UINT8 ? ; < Dct pointer - WrDatGrossH UINT8 ? ; < Write Data Gross delay high value - DqsRcvEnGrossL UINT8 ? ; < DQS Receive Enable Gross Delay low - - TrwtWB UINT8 ? ; < Non-SPD timing value for TrwtWB - CurrRcvrDctADelay UINT8 ? ; < for keep current RcvrEnDly - T1000 UINT16 ? ; < get the T1000 figure (cycle time (ns) * 1K) - DqsRcvEnPass UINT8 ? ; < for TrainRcvrEn UINT8 lane pass flag - DqsRcvEnSaved UINT8 ? ; < for TrainRcvrEn UINT8 lane saved flag - SeedPass1Remainder UINT8 ? ; < for Phy assisted DQS receiver enable training - - ClToNbFlag UINT8 ? ; < is used to restore ClLinesToNbDis bit after memory - NodeSysBase UINT32 ? ; < for channel interleave usage - RefRawCard UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of rawcards detected - CtrlWrd02 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 2 values per DIMM - CtrlWrd03 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 3 values per DIMM - CtrlWrd04 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 4 values per DIMM - CtrlWrd05 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 5 values per DIMM - CtrlWrd08 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 8 values per DIMM - - CsPresentDCT UINT16 ? ; < For each bit n 0..7, 1 = Chip-select n is present - DimmMirrorPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable - DimmSpdCse UINT8 ? ; < For each bit n 0..7, 1 = DIMM n SPD checksum error - DimmExclude UINT8 ? ; < For each bit n 0..7, 1 = DIMM n gets excluded - DimmYr06 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's year code <= 2006 - DimmWk2406 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June) - DimmPlPresent UINT8 ? ; < Bitmap indicating that Planar (1) or Stacked (0) Dimms are present. - DimmQrPresent UINT8 ? ; < QuadRank DIMM present? - DimmDrPresent UINT8 ? ; < Bitmap indicating that Dual Rank Dimms are present - DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present - Dimmx4Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved. - Dimmx8Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved. - Dimmx16Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved. - LrdimmPhysicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of Physical Ranks for LRDIMMs - LrDimmLogicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of LRDIMM Logical ranks in this configuration - LrDimmRankMult UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Rank Multipication factor per dimm. - - MemClkDisMap POINTER ? ; < This pointer will be set to point to an array that describes - ; < the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will - ; < base on this array to disable unused MemClk to save power. - ; < - ; < The array must have 8 entries. Each entry, which associates with - ; < one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to. - ; < Example: - ; < BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package - ; < is like below: - ; < Bit AM3/S1g3 pin name - ; < 0 M[B,A]_CLK_H/L[0] - ; < 1 M[B,A]_CLK_H/L[1] - ; < 2 M[B,A]_CLK_H/L[2] - ; < 3 M[B,A]_CLK_H/L[3] - ; < 4 M[B,A]_CLK_H/L[4] - ; < 5 M[B,A]_CLK_H/L[5] - ; < 6 M[B,A]_CLK_H/L[6] - ; < 7 M[B,A]_CLK_H/L[7] - ; < And platform has the following routing: - ; < CS0 M[B,A]_CLK_H/L[4] - ; < CS1 M[B,A]_CLK_H/L[2] - ; < CS2 M[B,A]_CLK_H/L[3] - ; < CS3 M[B,A]_CLK_H/L[5] - ; < Then MemClkDisMap should be pointed to the following array: - ; < CLK_2 CLK_3 CLK_4 CLK_5 - ; < 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00 - ; < Each entry of the array is the bitmask of 8 chip selects. - - CKETriMap POINTER ? ; < This pointer will be set to point to an array that describes - ; < the routing of CKE pins to the DIMMs' ranks. - ; < The array must have 2 entries. Each entry, which associates with - ; < one CKE pin, is a bitmap of 8 CS that that CKE is routed to. - ; < AGESA will base on this array to disable unused CKE pins to save power. - - ODTTriMap POINTER ? ; < This pointer will be set to point to an array that describes - ; < the routing of ODT pins to the DIMMs' ranks. - ; < The array must have 4 entries. Each entry, which associates with - ; < one ODT pin, is a bitmap of 8 CS that that ODT is routed to. - ; < AGESA will base on this array to disable unused ODT pins to save power. - - ChipSelTriMap POINTER ? ; < This pointer will be set to point to an array that describes - ; < the routing of chip select pins to the DIMMs' ranks. - ; < The array must have 8 entries. Each entry is a bitmap of 8 CS. - ; < AGESA will base on this array to disable unused Chip select pins to save power. - - ExtendTmp BOOLEAN ? ; < If extended temperature is supported on all dimms on a channel. - - Reserved UINT8 (100) DUP (?) ; < Reserved -CH_DEF_STRUCT ENDS - -; =============================================================================== - ; DCT Channel Timing Parameters - ; This data structure sets timings that are specific to the channel -; =============================================================================== -CH_TIMING_STRUCT STRUCT - DctDimmValid UINT16 ? ; < For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved. - DimmMirrorPresent UINT16 ? ; < For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved. - DimmSpdCse UINT16 ? ; < For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved. - DimmExclude UINT16 ? ; < For each bit n 0..3, 1 = DIMM n gets excluded because of no common voltage is found - CsPresent UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present - CsEnabled UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is enabled - CsTestFail UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present but disabled - CsTrainFail UINT16 ? ; < Bitmap showing which chipselects failed training - DIMM1KPage UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved. - DimmQrPresent UINT16 ? ; < QuadRank DIMM present? - DimmDrPresent UINT16 ? ; < Bitmap indicating that Dual Rank Dimms are present - DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present - Dimmx4Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved. - Dimmx8Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved. - Dimmx16Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved. - - DIMMTrcd UINT16 ? ; < Minimax Trcd*40 (ns) of DIMMs - DIMMTrp UINT16 ? ; < Minimax Trp*40 (ns) of DIMMs - DIMMTrtp UINT16 ? ; < Minimax Trtp*40 (ns) of DIMMs - DIMMTras UINT16 ? ; < Minimax Tras*40 (ns) of DIMMs - DIMMTrc UINT16 ? ; < Minimax Trc*40 (ns) of DIMMs - DIMMTwr UINT16 ? ; < Minimax Twr*40 (ns) of DIMMs - DIMMTrrd UINT16 ? ; < Minimax Trrd*40 (ns) of DIMMs - DIMMTwtr UINT16 ? ; < Minimax Twtr*40 (ns) of DIMMs - DIMMTfaw UINT16 ? ; < Minimax Tfaw*40 (ns) of DIMMs - TargetSpeed UINT16 ? ; < Target DRAM bus speed in MHz - Speed UINT16 ? ; < DRAM bus speed in MHz - ; < 400 (MHz) - ; < 533 (MHz) - ; < 667 (MHz) - ; < 800 (MHz) - ; < and so on... - CasL UINT8 ? ; < CAS latency DCT setting (busclocks) - Trcd UINT8 ? ; < DCT Trcd (busclocks) - Trp UINT8 ? ; < DCT Trp (busclocks) - Trtp UINT8 ? ; < DCT Trtp (busclocks) - Tras UINT8 ? ; < DCT Tras (busclocks) - Trc UINT8 ? ; < DCT Trc (busclocks) - Twr UINT8 ? ; < DCT Twr (busclocks) - Trrd UINT8 ? ; < DCT Trrd (busclocks) - Twtr UINT8 ? ; < DCT Twtr (busclocks) - Tfaw UINT8 ? ; < DCT Tfaw (busclocks) - Trfc0 UINT8 ? ; < DCT Logical DIMM0 Trfc - ; < 0 = 75ns (for 256Mb devs) - ; < 1 = 105ns (for 512Mb devs) - ; < 2 = 127.5ns (for 1Gb devs) - ; < 3 = 195ns (for 2Gb devs) - ; < 4 = 327.5ns (for 4Gb devs) - Trfc1 UINT8 ? ; < DCT Logical DIMM1 Trfc (see Trfc0 for format) - Trfc2 UINT8 ? ; < DCT Logical DIMM2 Trfc (see Trfc0 for format) - Trfc3 UINT8 ? ; < DCT Logical DIMM3 Trfc (see Trfc0 for format) - DctMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by this DCT. - SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode) - ; < FALSE = 1T - ; < TRUE = 2T - TrwtTO UINT8 ? ; < DCT TrwtTO (busclocks) - Twrrd UINT8 ? ; < DCT Twrrd (busclocks) - Twrwr UINT8 ? ; < DCT Twrwr (busclocks) - Trdrd UINT8 ? ; < DCT Trdrd (busclocks) - TrwtWB UINT8 ? ; < DCT TrwtWB (busclocks) - TrdrdSD UINT8 ? ; < DCT TrdrdSD (busclocks) - TwrwrSD UINT8 ? ; < DCT TwrwrSD (busclocks) - TwrrdSD UINT8 ? ; < DCT TwrrdSD (busclocks) - MaxRdLat UINT16 ? ; < Max Read Latency - WrDatGrossH UINT8 ? ; < Temporary variables must be removed - DqsRcvEnGrossL UINT8 ? ; < Temporary variables must be removed -CH_TIMING_STRUCT ENDS - -; =============================================================================== - ; Data for each DCT - ; This data structure defines data used to configure each DRAM controller -; =============================================================================== -DCT_STRUCT STRUCT - Dct UINT8 ? ; < Current Dct - Timings CH_TIMING_STRUCT {} ; < Channel Timing structure - ChData POINTER ? ; < Pointed to a dynamically allocated array of Channel structures - ChannelCount UINT8 ? ; < Number of channel per this DCT -DCT_STRUCT ENDS - - -; =============================================================================== - ; Data Structure defining each Die - ; This data structure contains information that is used to configure each Die -; =============================================================================== -DIE_STRUCT STRUCT - - ; Advanced: - - NodeId UINT8 ? ; < Node ID of current controller - SocketId UINT8 ? ; < Socket ID of this Die - DieId UINT8 ? ; < ID of this die relative to the socket - PciAddr PCI_ADDR {} ; < Pci bus and device number of this controller. - ErrCode AGESA_STATUS ? ; < Current error condition of Node - ; < 0x0 = AGESA_SUCCESS - ; < 0x1 = AGESA_UNSUPPORTED - ; < 0x2 = AGESA_BOUNDS_CHK - ; < 0x3 = AGESA_ALERT - ; < 0x4 = AGESA_WARNING - ; < 0x5 = AGESA_ERROR - ; < 0x6 = AGESA_CRITICAL - ; < 0x7 = AGESA_FATAL - ; < - ErrStatus BOOLEAN (EsbEOL) DUP (?) ; < Error Status bit Field - Status BOOLEAN (SbEOL) DUP (?) ; < Status bit Field - NodeMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node. - NodeSysBase UINT32 ? ; < Base[47:16] (system address) DRAM base address of this Node. - NodeHoleBase UINT32 ? ; < If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node - NodeSysLimit UINT32 ? ; < Base[47:16] (system address) DRAM limit address of this Node. - DimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is present. - ; < DIMM# Select Signal - ; < 0 MA0_CS_L[0, 1] - ; < 1 MB0_CS_L[0, 1] - ; < 2 MA1_CS_L[0, 1] - ; < 3 MB1_CS_L[0, 1] - ; < 4 MA2_CS_L[0, 1] - ; < 5 MB2_CS_L[0, 1] - ; < 6 MA3_CS_L[0, 1] - ; < 7 MB3_CS_L[0, 1] - DimmValid UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is valid and is / will be configured - RegDimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is registered DIMM - LrDimmPresent UINT32 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved. - DimmEccPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ECC capable. - DimmParPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable. - DimmTrainFail UINT16 ? ; < Bitmap showing which dimms failed training - ChannelTrainFail UINT16 ? ; < Bitmap showing the channel information about failed Chip Selects - ; < 0 in any bit field indicates Channel 0 - ; < 1 in any bit field indicates Channel 1 - Dct UINT8 ? ; < Need to be removed - ; < DCT pointer - GangedMode BOOLEAN ? ; < Ganged mode - ; < 0 = disabled - ; < 1 = enabled - LogicalCpuid CPU_LOGICAL_ID {} ; < The logical CPUID of the node - HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space. - HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space. - MLoad UINT8 ? ; < Need to be removed - ; < Number of devices loading MAA bus - MaxAsyncLat UINT8 ? ; < Legacy wrapper - ChbD3Rcvrdly UINT8 ? ; < Legacy wrapper - ChaMaxRdLat UINT16 ? ; < Max Read Latency (ns) for DCT 0 - ChbD3BcRcvrdly UINT8 ? ; < CHB DIMM 3 Check UINT8 Receiver Enable Delay - - DctData POINTER ? ; < Pointed to a dynamically allocated array of DCT_STRUCTs - DctCount UINT8 ? ; < Number of DCTs per this Die - Reserved UINT8 (16) DUP (?) ; < Reserved -DIE_STRUCT ENDS - -; ********************************************************************* -; * S3 Support structure -; ********************************************************************* - ; AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure -AMD_S3_PARAMS STRUCT - Signature UINT32 ? ; < "ASTR" for AMD Suspend-To-RAM - Version UINT16 ? ; < S3 Params version number - Flags UINT32 ? ; < Indicates operation - NvStorage POINTER ? ; < Pointer to memory critical save state data - NvStorageSize UINT32 ? ; < Size in bytes of the NvStorage region - VolatileStorage POINTER ? ; < Pointer to remaining AMD save state data - VolatileStorageSize UINT32 ? ; < Size in bytes of the VolatileStorage region -AMD_S3_PARAMS ENDS - -; =============================================================================== - ; MEM_PARAMETER_STRUCT - ; This data structure is used to pass wrapper parameters to the memory configuration code -; =============================================================================== -MEM_PARAMETER_STRUCT STRUCT - - ; Basic (Return parameters) - ; (This section contains the outbound parameters from the memory init code) - - GStatus BOOLEAN (GsbEOL) DUP (?) ; < Global Status bitfield - HoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping. - Sub4GCacheTop UINT32 ? ; < If not zero, the 32-bit top of cacheable memory. - SysLimit UINT32 ? ; < Limit[47:16] (system address) - DDR3Voltage DIMM_VOLTAGE ? ; < Find support voltage and send back to platform BIOS. - ; < 0 = 1.5v - ; < 1 = 1.35v - ; < 2 = 1.2v - ; < 0xFF = Mixed 1.5V and 1.2V in the system. 1.5V dimms get excluded - ; < from the system. - ; < - - MemData POINTER ? ; < Pointer to MEM_DATA_STRUCT - ; Advanced (Optional parameters) - ; Optional (all defaults values will be initialized by the - ; 'AmdMemInitDataStructDef' based on AMD defaults. It is up - ; to the IBV/OEM to change the defaults after initialization - ; but prior to the main entry to the memory code): - - ; Memory Map/Mgt. - - BottomIo UINT16 ? ; < Bottom of 32-bit IO space (8-bits) - ; < NV_BOTTOM_IO[7:0]=Addr[31:24] - MemHoleRemapping BOOLEAN ? ; < Memory Hole Remapping (1-bit) - ; < FALSE = disable - ; < TRUE = enable - - - ; Dram Timing - - UserTimingMode USER_MEMORY_TIMING_MODE ? ; < User Memclock Mode - - MemClockValue MEMORY_BUS_SPEED ? ; < Memory Clock Value - - ; Dram Configuration - - EnableBankIntlv BOOLEAN ? ; < Dram Bank (chip-select) Interleaving (1-bit) - ; < FALSE =disable (AMD default) - ; < TRUE =enable - EnableNodeIntlv BOOLEAN ? ; < Node Memory Interleaving (1-bit) - ; < FALSE = disable (AMD default) - ; < TRUE = enable - EnableChannelIntlv BOOLEAN ? ; < Channel Interleaving (1-bit) - ; < FALSE = disable (AMD default) - ; < TRUE = enable - ; ECC - - EnableEccFeature BOOLEAN ? ; < enable ECC error to go into MCE - ; < FALSE = disable (AMD default) - ; < TRUE = enable - ; Dram Power - - EnablePowerDown BOOLEAN ? ; < CKE based power down mode (1-bit) - ; < FALSE =disable (AMD default) - ; < TRUE =enable - ; Online Spare - - EnableOnLineSpareCtl BOOLEAN ? ; < Chip Select Spare Control bit 0: - ; < FALSE = disable Spare (AMD default) - ; < TRUE = enable Spare - TableBasedAlterations POINTER ? ; < Point to an array of data bytes describing desired modifications to register settings. - - PlatformMemoryConfiguration POINTER ? - ; < Points to a table that contains platform specific settings - ; < (i.e. MemClk routing, the number of DIMM slots per channel,...) - ; < AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that - ; < contains default conservative settings. Platform BIOS can either tweak - ; < DefaultPlatformMemoryConfiguration or reassign this pointer to its own table. - ; < - EnableParity BOOLEAN ? ; < Parity control - ; < TRUE = enable - ; < FALSE = disable (AMD default) - EnableBankSwizzle BOOLEAN ? ; < BankSwizzle control - ; < FALSE = disable - ; < TRUE = enable (AMD default) - EnableMemClr BOOLEAN ? ; < Memory Clear functionality control - ; < FALSE = disable - ; < TRUE = enable (AMD default) - ; Uma Configuration - - UmaMode UMA_MODE ? ; < Uma Mode - ; < 0 = None - ; < 1 = Specified - ; < 2 = Auto - UmaSize UINT32 ? ; < The size of shared graphics dram (16-bits) - ; < NV_UMA_Size[31:0]=Addr[47:16] - ; < - UmaBase UINT32 ? ; < The allocated Uma base address (32-bits) - ; < NV_UMA_Base[31:0]=Addr[47:16] - ; < - - ; Memory Restore Feature - - MemRestoreCtl BOOLEAN ? ; < Memory context restore control - ; < FALSE = perform memory init as normal (AMD default) - ; < TRUE = restore memory context and skip training. This requires - ; < MemContext is valid before AmdInitPost - SaveMemContextCtl BOOLEAN ? ; < Control switch to save memory context at the end of MemAuto - ; < TRUE = AGESA will setup MemContext block before exit AmdInitPost - ; < FALSE = AGESA will not setup MemContext block. Platform is - ; < expected to call S3Save later in POST if it wants to - ; < use memory context restore feature. - MemContext AMD_S3_PARAMS {} ; < Memory context block describes the data that platform needs to - ; < save and restore for memory context restore feature to work. - ; < It uses the subset of S3Save block to save/restore. Hence platform - ; < may save only S3 block and uses it for both S3 resume and - ; < memory context restore. - ; < - If MemRestoreCtl is TRUE, platform needs to pass in MemContext - ; < before AmdInitPost. - ; < - If SaveMemContextCtl is TRUE, platform needs to save MemContext - ; < right after AmdInitPost. -MEM_PARAMETER_STRUCT ENDS - - -; =============================================================================== - ; Function definition - ; This data structure passes function pointers to the memory configuration code. - ; The wrapper can use this structure with customized versions -; ================================================================================ -MEM_FUNCTION_STRUCT STRUCT - - ; PUBLIC required Internal functions - - amdMemGetPsCfgU POINTER ? ; < Proc for Unbuffered DIMMs, platform specific - amdMemGetPsCfgR POINTER ? ; < Proc for Registered DIMMs, platform specific - - ; PUBLIC optional functions - - amdMemEccInit POINTER ? ; < NB proc for ECC feature - amdMemChipSelectInterleaveInit POINTER ? ; < NB proc for CS interleave feature - amdMemDctInterleavingInit POINTER ? ; < NB proc for Channel interleave feature - amdMemMctInterleavingInit POINTER ? ; < NB proc for Node interleave feature - amdMemParallelTraining POINTER ? ; < NB proc for parallel training feature - amdMemEarlySampleSupport POINTER ? ; < NB code for early sample support feature - amdMemMultiPartInitSupport POINTER ? ; < NB code for 'multi-part' - amdMemOnlineSpareSupport POINTER ? ; < NB code for On-Line Spare feature - amdMemUDimmInit POINTER ? ; < NB code for UDIMMs - amdMemRDimmInit POINTER ? ; < NB code for RDIMMs - amdMemLrDimmInit POINTER ? ; < NB code for LRDIMMs - - Reserved UINT32 (100) DUP (?) ; < Reserved for later function definition -MEM_FUNCTION_STRUCT ENDS - -; =============================================================================== - ; Socket Structure - -; =============================================================================== -MEM_SOCKET_STRUCT STRUCT - ChannelPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels training data - - TimingsPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels timing data - -MEM_SOCKET_STRUCT ENDS - -; =============================================================================== - ; MEM_DATA_STRUCT -; =============================================================================== -MEM_DATA_STRUCT STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header - - ParameterListPtr POINTER ? ; < List of input Parameters - - FunctionList MEM_FUNCTION_STRUCT {} ; < List of function Pointers - - GetPlatformCfg POINTER (MAX_PLATFORM_TYPES) DUP (?) ; < look-up platform info - - ErrorHandling POINTER ? ; < Error Handling - - ; SocketList is a shortcut for IBVs to retrieve training - ; and timing data for each channel indexed by socket/channel, - ; eliminating their need to parse die/dct/channel etc. - ; It contains pointers to the populated data structures for - ; each channel and skips the channel structures that are - ; unpopulated. In the case of channels sharing the same DCT, - ; the pTimings pointers will point to the same DCT Timing data. - - SocketList MEM_SOCKET_STRUCT (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Socket list for memory code - - DiesPerSystem POINTER ? ; < Pointed to an array of DIE_STRUCTs - DieCount UINT8 ? ; < Number of MCTs in the system. - - SpdDataStructure POINTER ? ; < Pointer to SPD Data structure - - PlatFormConfig POINTER ? ; < Pointer to Platform profile/build option config structure - - IsFlowControlSupported BOOLEAN ? ; < Indicates if flow control is supported - - TscRate UINT32 ? ; < The rate at which the TSC increments in megahertz. - -MEM_DATA_STRUCT ENDS - -; =============================================================================== -; UMA_INFO_STRUCT -; =============================================================================== -UMA_INFO STRUCT - UmaBase UINT64 ? ; < UmaBase[63:0] = Addr[63:0] - UmaSize UINT32 ? ; < UmaSize[31:0] = Addr[31:0] - UmaAttributes UINT32 ? ; < Indicate the attribute of Uma - UmaMode UINT8 ? ; < Indicate the mode of Uma - MemClock UINT16 ? ; < Indicate memory running speed in MHz - Reserved UINT8 (3) DUP (?) ; < Reserved for future usage -UMA_INFO ENDS - - ; AGESA MEMORY ERRORS - - ; AGESA_ALERT Memory Errors -MEM_ALERT_USER_TMG_MODE_OVERRULED EQU 04010000h ; < TIMING_MODE_SPECIFIC is requested but - ; < cannot be applied to current configurations. -MEM_ALERT_ORG_MISMATCH_DIMM EQU 04010100h ; < DIMM organization miss-match -MEM_ALERT_BK_INT_DIS EQU 04010200h ; < Bank interleaving disable for internal issue - - ; AGESA_ERROR Memory Errors -MEM_ERROR_NO_DQS_POS_RD_WINDOW EQU 04010300h ; < No DQS Position window for RD DQS -MEM_ERROR_SMALL_DQS_POS_RD_WINDOW EQU 04020300h ; < Small DQS Position window for RD DQS -MEM_ERROR_NO_DQS_POS_WR_WINDOW EQU 04030300h ; < No DQS Position window for WR DQS -MEM_ERROR_SMALL_DQS_POS_WR_WINDOW EQU 04040300h ; < Small DQS Position window for WR DQS -MEM_ERROR_ECC_DIS EQU 04010400h ; < ECC has been disabled as a result of an internal issue -MEM_ERROR_DIMM_SPARING_NOT_ENABLED EQU 04010500h ; < DIMM sparing has not been enabled for an internal issues -MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE EQU 04050300h ; < Receive Enable value is too large -MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW EQU 04060300h ; < There is no DQS receiver enable window -MEM_ERROR_DRAM_ENABLED_TIME_OUT EQU 04010600h ; < Time out when polling DramEnabled bit -MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT EQU 04010700h ; < Time out when polling DctAccessDone bit -MEM_ERROR_SEND_CTRL_WORD_TIME_OUT EQU 04010800h ; < Time out when polling SendCtrlWord bit -MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT EQU 04010900h ; < Time out when polling PrefDramTrainMode bit -MEM_ERROR_ENTER_SELF_REF_TIME_OUT EQU 04010A00h ; < Time out when polling EnterSelfRef bit -MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT EQU 04010B00h ; < Time out when polling FreqChgInProg bit -MEM_ERROR_EXIT_SELF_REF_TIME_OUT EQU 04020A00h ; < Time out when polling ExitSelfRef bit -MEM_ERROR_SEND_MRS_CMD_TIME_OUT EQU 04010C00h ; < Time out when polling SendMrsCmd bit -MEM_ERROR_SEND_ZQ_CMD_TIME_OUT EQU 04010D00h ; < Time out when polling SendZQCmd bit -MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT EQU 04010E00h ; < Time out when polling DctExtraAccessDone bit -MEM_ERROR_MEM_CLR_BUSY_TIME_OUT EQU 04010F00h ; < Time out when polling MemClrBusy bit -MEM_ERROR_MEM_CLEARED_TIME_OUT EQU 04020F00h ; < Time out when polling MemCleared bit -MEM_ERROR_FLUSH_WR_TIME_OUT EQU 04011000h ; < Time out when polling FlushWr bit -MEM_ERROR_MAX_LAT_NO_WINDOW EQU 04070300h ; < Fail to find pass during Max Rd Latency training -MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL EQU 04080300h ; < Fail to launch training code on an AP -MEM_ERROR_PARALLEL_TRAINING_TIME_OUT EQU 04090300h ; < Fail to finish parallel training -MEM_ERROR_NO_ADDRESS_MAPPING EQU 04011100h ; < No address mapping found for a dimm -MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT EQU 040A0300h ; < There is no DQS receiver enable window and the value is equal to the largest value -MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE EQU 040B0300h ; < Receive Enable value is too large and is 1 less than limit -MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR EQU 04011200h ; < SPD Checksum error for NV_SPDCHK_RESTRT -MEM_ERROR_NO_CHIPSELECT EQU 04011300h ; < No chipselects found -MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM EQU 04011500h ; < Unbuffered dimm is not supported at 333MHz -MEM_ERROR_WL_PRE_OUT_OF_RANGE EQU 040C0300h ; < Returned PRE value during write levelization was out of range - - ; AGESA_WARNING Memory Errors - MEM_WARNING_UNSUPPORTED_QRDIMM EQU 04011600h ; < QR DIMMs detected but not supported - MEM_WARNING_UNSUPPORTED_UDIMM EQU 04021600h ; < U DIMMs detected but not supported - MEM_WARNING_UNSUPPORTED_SODIMM EQU 04031600h ; < SO-DIMMs detected but not supported - MEM_WARNING_UNSUPPORTED_X4DIMM EQU 04041600h ; < x4 DIMMs detected but not supported - MEM_WARNING_UNSUPPORTED_RDIMM EQU 04051600h ; < R DIMMs detected but not supported - MEM_WARNING_UNSUPPORTED_LRDIMM EQU 04061600h ; < LR DIMMs detected but not supported - - MEM_WARNING_EMP_NOT_SUPPORTED EQU 04011700h ; < Processor is not capable for EMP - MEM_WARNING_EMP_CONFLICT EQU 04021700h ; < EMP cannot be enabled if channel interleaving, - ; < bank interleaving, or bank swizzle is enabled. - MEM_WARNING_EMP_NOT_ENABLED EQU 04031700h ; < Memory size is not power of two. - MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED EQU 04011800h ; < Performance has been enabled, but battery life is preferred. - MEM_WARNING_NO_SPDTRC_FOUND EQU 04011900h ; < No Trc timing value found in SPD of a dimm. - MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED EQU 04012000h ; < Node Interleaveing Requested, but could not be enabled - MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED EQU 04012100h ; < Channel Interleaveing Requested, but could not be enabled - MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED EQU 04012200h ; < Bank Interleaveing Requested, but could not be enabled - MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED EQU 04012300h ; < Voltage 1.35 determined, but could not be supported - - ; AGESA_FATAL Memory Errors - MEM_ERROR_MINIMUM_MODE EQU 04011A00h ; < Running in minimum mode - MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM EQU 04011B00h ; < DIMM modules are miss-matched - MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM EQU 04011C00h ; < No DIMMs have been found on system - MEM_ERROR_MISMATCH_DIMM_CLOCKS EQU 04011D00h ; < DIMM clocks miss-matched - MEM_ERROR_NO_CYC_TIME EQU 04011E00h ; < No cycle time found - MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS EQU 04011F00h ; < Heap allocation error with dynamic storing of trained timings - MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs EQU 04021F00h ; < Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT - MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV EQU 04031F00h ; < Heap allocation error with REMOTE_TRAINING_ENV - MEM_ERROR_HEAP_ALLOCATE_FOR_SPD EQU 04041F00h ; < Heap allocation error for SPD data - MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA EQU 04051F00h ; < Heap allocation error for RECEIVED_DATA during parallel training - MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS EQU 04061F00h ; < Heap allocation error for S3 "SPECIAL_CASE_REGISTER" - MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA EQU 04071F00h ; < Heap allocation error for Training Data - MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK EQU 04081F00h ; < Heap allocation error for DIMM Identify "MEM_NB_BLOCK - MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM EQU 04022300h ; < No Constructor for DIMM Identify - - - ; AGESA_CRITICAL Memory Errors - MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 EQU 04091F00h ; < Heap allocation error for DMI table for DDR3 - MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 EQU 040A1F00h ; < Heap allocation error for DMI table for DDR2 - MEM_ERROR_UNSUPPORTED_DIMM_CONFIG EQU 04011400h ; < Dimm population is not supported - - -; ---------------------------------------------------------------------------- -; * -; * END OF MEMORY-SPECIFIC DATA STRUCTURES -; * -; *---------------------------------------------------------------------------- -; - - -; ---------------------------------------------------------------------------- -; * -; * CPU RELATED DEFINITIONS -; * -; *---------------------------------------------------------------------------- -; - -; CPU Event definitions. - -; Defines used to filter CPU events based on functional blocks -CPU_EVENT_PM_EVENT_MASK EQU 0FF00FF00h -CPU_EVENT_PM_EVENT_CLASS EQU 008000400h - -;================================================================ -; CPU General events -; Heap allocation (AppFunction = 01h) -CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT EQU 008000100h -CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED EQU 008010100h -CPU_ERROR_HEAP_IS_FULL EQU 008020100h -CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED EQU 008030100h -CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT EQU 008040100h -; BrandId (AppFunction = 02h) -CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE EQU 008000200h -; Micro code patch (AppFunction = 03h) -CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED EQU 008000300h -; Power management (AppFunction = 04h) -CPU_EVENT_PM_PSTATE_OVERCURRENT EQU 008000400h -CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT EQU 008010400h -CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE EQU 008020400h -CPU_ERROR_PM_NB_PSTATE_MISMATCH EQU 008030400h -; BIST (AppFunction = 05h) -CPU_EVENT_BIST_ERROR EQU 008000500h -;================================================================= -; CPU Feature events -; Execution cache (AppFunction = 21h) -; AGESA_CACHE_SIZE_REDUCED 2101 -; AGESA_CACHE_REGIONS_ACROSS_1MB 2102 -; AGESA_CACHE_REGIONS_ACROSS_4GB 2103 -; AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104 -; AGESA_CACHE_START_ADDRESS_LESS_D0000 2105 -; AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106 -; AGESA_DEALLOCATE_CACHE_REGIONS 2107 -CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR EQU 008002100h -; Core Leveling (AppFunction = 22h) -CPU_WARNING_ADJUSTED_LEVELING_MODE EQU 008002200h -; HT Assist (AppFunction = 23h) -CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG EQU 008002300h - -; CPU Build Configuration structures and definitions - -; Build Configuration values for BLDGCFG_AP_MTRR_SETTINGS -AP_MTRR_SETTINGS STRUCT - MsrAddr UINT32 ? ; < Fixed-Sized MTRR address - MsrData UINT64 ? ; < MTRR Settings -AP_MTRR_SETTINGS ENDS - -AMD_AP_MTRR_FIX64k_00000 EQU 000000250h -AMD_AP_MTRR_FIX16k_80000 EQU 000000258h -AMD_AP_MTRR_FIX16k_A0000 EQU 000000259h -AMD_AP_MTRR_FIX4k_C0000 EQU 000000268h -AMD_AP_MTRR_FIX4k_C8000 EQU 000000269h -AMD_AP_MTRR_FIX4k_D0000 EQU 00000026Ah -AMD_AP_MTRR_FIX4k_D8000 EQU 00000026Bh -AMD_AP_MTRR_FIX4k_E0000 EQU 00000026Ch -AMD_AP_MTRR_FIX4k_E8000 EQU 00000026Dh -AMD_AP_MTRR_FIX4k_F0000 EQU 00000026Eh -AMD_AP_MTRR_FIX4k_F8000 EQU 00000026Fh -CPU_LIST_TERMINAL EQU 0FFFFFFFFh - -; *********************************************************************** -; * -; * AGESA interface Call-Out function parameter structures -; * -; ********************************************************************** - - ; Parameters structure for interface call-out AgesaAllocateBuffer -AGESA_BUFFER_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Standard header - BufferLength UINT32 ? ; < Size of buffer to allocate - BufferHandle UINT32 ? ; < Identifier or name for the buffer - BufferPointer POINTER ? ; < location of the created buffer -AGESA_BUFFER_PARAMS ENDS - - ; Parameters structure for interface call-out AgesaRunCodeOnAp -AP_EXE_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Standard header - FunctionNumber UINT32 ? ; < Index of the procedure to execute - RelatedDataBlock POINTER ? ; < Location of data structure the procedure will use - RelatedBlockLength UINT32 ? ; < Size of the related data block -AP_EXE_PARAMS ENDS - - ; Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery -AGESA_READ_SPD_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < standard header - SocketId UINT8 ? ; < Address of SPD - socket ID - MemChannelId UINT8 ? ; < Address of SPD - memory channel ID - DimmId UINT8 ? ; < Address of SPD - DIMM ID - Buffer POINTER ? ; < Location where to place the SPD content - MemData POINTER ? ; < Location of the MemData structure, for reference -AGESA_READ_SPD_PARAMS ENDS - - ; Buffer Handles - AMD_DMI_INFO_BUFFER_HANDLE EQU 000D000h ; < Assign 0x000D000 buffer handle to DMI function - AMD_PSTATE_DATA_BUFFER_HANDLE EQU 000D001h ; < Assign 0x000D001 buffer handle to Pstate data - AMD_PSTATE_ACPI_BUFFER_HANDLE EQU 000D002h ; < Assign 0x000D002 buffer handle to Pstate table - AMD_BRAND_ID_BUFFER_HANDLE EQU 000D003h ; < Assign 0x000D003 buffer handle to Brand ID - AMD_ACPI_SLIT_BUFFER_HANDLE EQU 000D004h ; < Assign 0x000D004 buffer handle to SLIT function - AMD_SRAT_INFO_BUFFER_HANDLE EQU 000D005h ; < Assign 0x000D005 buffer handle to SRAT function - AMD_WHEA_BUFFER_HANDLE EQU 000D006h ; < Assign 0x000D006 buffer handle to WHEA function - AMD_S3_INFO_BUFFER_HANDLE EQU 000D007h ; < Assign 0x000D007 buffer handle to S3 function - AMD_S3_NB_INFO_BUFFER_HANDLE EQU 000D008h ; < Assign 0x000D008 buffer handle to S3 NB device info - AMD_ACPI_ALIB_BUFFER_HANDLE EQU 000D009h ; < Assign 0x000D009 buffer handle to ALIB SSDT table -AMD_BUFFER_HANDLE TEXTEQU <DWORD> -; *********************************************************************** -; * -; * AGESA interface Call-Out function prototypes -; * -; ********************************************************************** - -; *********************************************************************** -; * -; * AGESA interface structure definition and function prototypes -; * -; ********************************************************************** - -; ********************************************************************* -; * Platform Configuration: The parameters in boot branch function -; ********************************************************************* - -; The possible platform control flow settings. - Nfcm EQU 0 ; < Normal Flow Control Mode. - UmaDr EQU 1 ; < UMA using Display Refresh flow control. - UmaIfcm EQU 2 ; < UMA using Isochronous Flow Control. - Ifcm EQU 3 ; < Isochronous Flow Control Mode (other than for UMA). - Iommu EQU 4 ; < An IOMMU is in use in the system. - MaxControlFlow EQU 5 ; < Not a control flow mode, use for limit checking. -PLATFORM_CONTROL_FLOW TEXTEQU <DWORD> - -; Platform Deemphasis Levels. - DeemphasisLevelNone EQU 0 ; < No Deemphasis. - DeemphasisLevelMinus3 EQU 1 ; < Minus 3 db deemphasis. - DeemphasisLevelMinus6 EQU 2 ; < Minus 6 db deemphasis. - DeemphasisLevelMinus8 EQU 3 ; < Minus 8 db deemphasis. - DeemphasisLevelMinus11 EQU 4 ; < Minus 11 db deemphasis. - DeemphasisLevelMinus11pre8 EQU 5 ; < Minus 11, Minus 8 precursor db deemphasis. - DcvLevelNone EQU 16 ; < No DCV Deemphasis. - DcvLevelMinus2 EQU 17 ; < Minus 2 db DCV deemphasis. - DcvLevelMinus3 EQU 18 ; < Minus 3 db DCV deemphasis. - DcvLevelMinus5 EQU 19 ; < Minus 5 db DCV deemphasis. - DcvLevelMinus6 EQU 20 ; < Minus 6 db DCV deemphasis. - DcvLevelMinus7 EQU 21 ; < Minus 7 db DCV deemphasis. - DcvLevelMinus8 EQU 22 ; < Minus 8 db DCV deemphasis. - DcvLevelMinus9 EQU 23 ; < Minus 9 db DCV deemphasis. - DcvLevelMinus11 EQU 24 ; < Minus 11 db DCV deemphasis. - MaxPlatformDeemphasisLevel EQU 25 ; < Not a deemphasis level, use for limit checking. -PLATFORM_DEEMPHASIS_LEVEL TEXTEQU <DWORD> - -; Provide Deemphasis Levels for HT Links. -; -; For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will -; be checked for a match. The item matches for a Socket, Link if the link frequency is -; is in the inclusive range HighFreq:LoFreq. -; AGESA does not set deemphasis in IO devices, only in processors. - -CPU_HT_DEEMPHASIS_LEVEL STRUCT - ; Match fields - Socket UINT8 ? ; < One Socket on which this Link is located - Link UINT8 ? ; < The Link on this Processor. - LoFreq UINT8 ? ; < If the link is set to this frequency or greater, apply these levels, and - HighFreq UINT8 ? ; < If the link is set to this frequency or less, apply these levels. - ; Value fields - ReceiverDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The deemphasis level for this link - DcvDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The DCV, or far transmitter deemphasis level. -CPU_HT_DEEMPHASIS_LEVEL ENDS - -; The possible platform power policy settings. - Performance EQU 0 ; < Optimize for performance. - BatteryLife EQU 1 ; < Optimize for battery life. - MaxPowerPolicy EQU 2 ; < Not a power policy mode, use for limit checking. -PLATFORM_POWER_POLICY TEXTEQU <DWORD> - -; Platform performance settings for optimized settings. -; Several configuration settings for the processor depend upon other parts and -; general designer choices for the system. The determination of these data points -; is not standard for all platforms, so the host environment needs to provide these -; to specify how the system is to be configured. -PERFORMANCE_PROFILE STRUCT - PlatformControlFlowMode PLATFORM_CONTROL_FLOW ? ; < The platform's control flow mode for optimum platform performance. - UseHtAssist BOOLEAN ? ; < HyperTransport link traffic optimization. - UseAtmMode BOOLEAN ? ; < HyperTransport link traffic optimization. - Use32ByteRefresh BOOLEAN ? ; < Display Refresh traffic generates 32 byte requests. - UseVariableMctIsocPriority BOOLEAN ? ; < The Memory controller will be set to Variable Isoc Priority. - PlatformPowerPolicy PLATFORM_POWER_POLICY ? ; < The platform's desired power policy -PERFORMANCE_PROFILE ENDS - -; Platform settings that describe the voltage regulator modules of the system. -; Many power management settings are dependent upon the characteristics of the -; on-board voltage regulator module (VRM). The host environment needs to provide -; these to specify how the system is to be configured. -PLATFORM_VRM_CONFIGURATION STRUCT - CurrentLimit UINT32 ? ; < Vrm Current Limit. - LowPowerThreshold UINT32 ? ; < Vrm Low Power Threshold. - SlewRate UINT32 ? ; < Vrm Slew Rate. - AdditionalDelay UINT32 ? ; < Vrm Additional Delay. - HiSpeedEnable BOOLEAN ? ; < Select high speed VRM. - InrushCurrentLimit UINT32 ? ; < Vrm Inrush Current Limit. -PLATFORM_VRM_CONFIGURATION ENDS - -; The VRM types to characterize. - CoreVrm EQU 0 ; < VDD plane. - NbVrm EQU 1 ; < VDDNB plane. - MaxVrmType EQU 2 ; < Not a valid VRM type, use for limit checking. -PLATFORM_VRM_TYPE TEXTEQU <DWORD> - -; Build Option/Configuration Boolean Structure -BUILD_OPT_CFG STRUCT - ; Build Option Area - VersionString AMD_CODE_HEADER {} ; < AMD embedded code version string - OptionUDimms BOOLEAN ? ; < UDIMMS - OptionRDimms BOOLEAN ? ; < RDIMMS - OptionLrDimms BOOLEAN ? ; < LRDIMMS - OptionEcc BOOLEAN ? ; < ECC - OptionBankInterleave BOOLEAN ? ; < BANK_INTERLEAVE - OptionDctInterleave BOOLEAN ? ; < DCT_INTERLEAVE - OptionNodeInterleave BOOLEAN ? ; < NODE_INTERLEAVE - OptionParallelTraining BOOLEAN ? ; < PARALLEL_TRAINING - OptionOnlineSpare BOOLEAN ? ; < ONLINE_SPARE - OptionMemRestore BOOLEAN ? ; < MEM CONTEXT RESTORE - OptionMultisocket BOOLEAN ? ; < MULTISOCKET - OptionAcpiPstates BOOLEAN ? ; < ACPI_PSTATES - OptionSrat BOOLEAN ? ; < SRAT - OptionSlit BOOLEAN ? ; < SLIT - OptionWhea BOOLEAN ? ; < WHEA - OptionDmi BOOLEAN ? ; < DMI - OptionEarlySamples BOOLEAN ? ; < EARLY_SAMPLES - OptionAddrToCsTranslator BOOLEAN ? ; < ADDR_TO_CS_TRANSLATOR - - ; Build Configuration Area - CfgPciMmioAddress UINT64 ? ; < PciMmioBase - CfgPciMmioSize UINT32 ? ; < PciMmioSize - CfgPlatVrmCfg PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules. - CfgPlatNumIoApics UINT32 ? ; < PlatformApicIoNumber - CfgMemInitPstate UINT32 ? ; < MemoryInitPstate - CfgPlatformC1eMode PLATFORM_C1E_MODES ? ; < PlatformC1eMode - CfgPlatformC1eOpData UINT32 ? ; < PlatformC1eOpData - CfgPlatformC1eOpData1 UINT32 ? ; < PlatformC1eOpData1 - CfgPlatformC1eOpData2 UINT32 ? ; < PlatformC1eOpData2 - CfgPlatformCStateMode PLATFORM_CSTATE_MODES ? ; < PlatformCStateMode - CfgPlatformCStateOpData UINT32 ? ; < PlatformCStateOpData - CfgPlatformCStateIoBaseAddress UINT16 ? ; < PlatformCStateIoBaseAddress - CfgPlatformCpbMode PLATFORM_CPB_MODES ? ; < PlatformCpbMode - CfgCoreLevelingMode UINT32 ? ; < CoreLevelingCofig - CfgPerformanceProfile PERFORMANCE_PROFILE {} ; < The platform's control flow mode and platform performance settings. - CfgPlatformDeemphasisList POINTER ? ; < HT Deemphasis - CfgAmdPlatformType UINT32 ? ; < AmdPlatformType - CfgAmdPstateCapValue UINT32 ? ; < Amd pstate ceiling enabling deck - - CfgMemoryBusFrequencyLimit MEMORY_BUS_SPEED ? ; < Memory Bus Frequency Limit - CfgMemoryModeUnganged BOOLEAN ? ; < Memory Mode Unganged - CfgMemoryQuadRankCapable BOOLEAN ? ; < Memory Quad Rank Capable - CfgMemoryQuadrankType QUANDRANK_TYPE ? ; < Memory Quadrank Type - CfgMemoryRDimmCapable BOOLEAN ? ; < Memory RDIMM Capable - CfgMemoryLRDimmCapable BOOLEAN ? ; < Memory LRDIMM Capable - CfgMemoryUDimmCapable BOOLEAN ? ; < Memory UDIMM Capable - CfgMemorySODimmCapable BOOLEAN ? ; < Memory SODimm Capable - CfgMemoryEnableBankInterleaving BOOLEAN ? ; < Memory Enable Bank Interleaving - CfgMemoryEnableNodeInterleaving BOOLEAN ? ; < Memory Enable Node Interleaving - CfgMemoryChannelInterleaving BOOLEAN ? ; < Memory Channel Interleaving - CfgMemoryPowerDown BOOLEAN ? ; < Memory Power Down - CfgPowerDownMode POWER_DOWN_MODE ? ; < Power Down Mode - CfgOnlineSpare BOOLEAN ? ; < Online Spare - CfgMemoryParityEnable BOOLEAN ? ; < Memory Parity Enable - CfgBankSwizzle BOOLEAN ? ; < Bank Swizzle - CfgTimingModeSelect USER_MEMORY_TIMING_MODE ? ; < Timing Mode Select - CfgMemoryClockSelect MEMORY_BUS_SPEED ? ; < Memory Clock Select - CfgDqsTrainingControl BOOLEAN ? ; < Dqs Training Control - CfgIgnoreSpdChecksum BOOLEAN ? ; < Ignore Spd Checksum - CfgUseBurstMode BOOLEAN ? ; < Use Burst Mode - CfgMemoryAllClocksOn BOOLEAN ? ; < Memory All Clocks On - CfgEnableEccFeature BOOLEAN ? ; < Enable ECC Feature - CfgEccRedirection BOOLEAN ? ; < ECC Redirection - CfgScrubDramRate UINT16 ? ; < Scrub Dram Rate - CfgScrubL2Rate UINT16 ? ; < Scrub L2Rate - CfgScrubL3Rate UINT16 ? ; < Scrub L3Rate - CfgScrubIcRate UINT16 ? ; < Scrub Ic Rate - CfgScrubDcRate UINT16 ? ; < Scrub Dc Rate - CfgEccSyncFlood BOOLEAN ? ; < ECC Sync Flood - CfgEccSymbolSize UINT16 ? ; < ECC Symbol Size - CfgHeapDramAddress UINT64 ? ; < Heap contents will be temporarily stored in this address during the transition - CfgNodeMem1GBAlign BOOLEAN ? ; < Node Mem 1GB boundary Alignment - CfgS3LateRestore BOOLEAN ? ; < S3 Late Restore - CfgAcpiPstateIndependent BOOLEAN ? ; < PSD method dependent/Independent - CfgApMtrrSettingsList POINTER ? ; < The AP's MTRR settings before final halt - CfgUmaMode UMA_MODE ? ; < Uma Mode - CfgUmaSize UINT32 ? ; < Uma Size [31:0]=Addr[47:16] - CfgUmaAbove4G BOOLEAN ? ; < Uma Above 4G Support - CfgUmaAlignment UMA_ALIGNMENT ? ; < Uma alignment - CfgProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope - CfgProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name. - CfgProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name. - CfgGnbHdAudio UINT8 ? ; < Gnb HD Audio Enable - CfgAbmSupport UINT8 ? ; < ABM support - CfgDynamicRefreshRate UINT8 ? ; < Dynamic refresh rate - CfgLcdBackLightControl UINT16 ? ; < Lcd back light control - CfgGnb3dStereoPinIndex UINT8 ? ; < 3D Stereo Pin ID - CfgTempPcieMmioBaseAddress UINT32 ? ; < Temp pcie MMIO base address - CfgGnbIGPUSSID UINT32 ? ; < Gnb internal GPU SSID - CfgGnbHDAudioSSID UINT32 ? ; < Gnb HD Audio SSID - CfgGnbPcieSSID UINT32 ? ; < Gnb PCIe SSID - CfgLvdsSpreadSpectrum UINT16 ? ; < Lvds Spread Spectrum. Build-time customizable only - CfgLvdsSpreadSpectrumRate UINT16 ? ; < Lvds Spread Spectrum Rate. Build-time customizable only - Reserved BOOLEAN ? ; < reserved... -BUILD_OPT_CFG ENDS - - ; A structure containing platform specific operational characteristics. This - ; structure is initially populated by the initializer with a copy of the same - ; structure that was created at build time using the build configuration controls. -PLATFORM_CONFIGURATION STRUCT - PlatformProfile PERFORMANCE_PROFILE {} ; < Several configuration settings for the processor. - PlatformDeemphasisList POINTER ? ; < Deemphasis levels for the platform's HT links. - CoreLevelingMode UINT8 ? ; < Indicates how to balance the number of cores per processor. - C1eMode PLATFORM_C1E_MODES ? ; < Specifies the method of C1e enablement - Disabled, HW, or message based. - C1ePlatformData UINT32 ? ; < If C1eMode is HW, specifies the P_LVL3 I/O port of the platform. - C1ePlatformData1 UINT32 ? ; < If C1eMode is SW, specifies the address of chipset's SMI command port. - C1ePlatformData2 UINT32 ? ; < If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source. - CStateMode PLATFORM_CSTATE_MODES ? ; < Specifies the method of C-State enablement - Disabled, or C6. - CStatePlatformData UINT32 ? ; < This element specifies some pertinent data needed for the operation of the Cstate feature - ; < If CStateMode is CStateModeC6, this item is reserved - CStateIoBaseAddress UINT16 ? ; < This item specifies a free block of 8 consecutive bytes of I/O ports that - ; < can be used to allow the CPU to enter Cstates. - CpbMode PLATFORM_CPB_MODES ? ; < Specifies the method of core performance boost enablement - Disabled, or Auto. - UserOptionDmi BOOLEAN ? ; < When set to TRUE, the DMI data table is generated. - UserOptionPState BOOLEAN ? ; < When set to TRUE, the PState data tables are generated. - UserOptionSrat BOOLEAN ? ; < When set to TRUE, the SRAT data table is generated. - UserOptionSlit BOOLEAN ? ; < When set to TRUE, the SLIT data table is generated. - UserOptionWhea BOOLEAN ? ; < When set to TRUE, the WHEA data table is generated. - PowerCeiling UINT32 ? ; < P-State Ceiling Enabling Deck - Max power milli-watts. - ForcePstateIndependent BOOLEAN ? ; < P-State _PSD independence or dependence. - NumberOfIoApics UINT32 ? ; < Number of I/O APICs in the system - VrmProperties PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules. - ProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope - ProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name. - ProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name. - GnbHdAudio UINT8 ? ; < Control GFX HD Audio controller(Used for HDMI and DP display output), - ; < essentially it enables function 1 of graphics device. - ; < @li 0 = HD Audio disable - ; < @li 1 = HD Audio enable - AbmSupport UINT8 ? ; < Automatic adjust LVDS/eDP Back light level support.It is - ; < characteristic specific to display panel which used by platform design. - ; < @li 0 = ABM support disabled - ; < @li 1 = ABM support enabled - DynamicRefreshRate UINT8 ? ; < Adjust refresh rate on LVDS/eDP. - LcdBackLightControl UINT16 ? ; < The PWM frequency to LCD backlight control. - ; < If equal to 0 backlight not controlled by iGPU. -PLATFORM_CONFIGURATION ENDS - - -; ********************************************************************* -; * Structures for: AmdInitLate -; ********************************************************************* - PROC_VERSION_LENGTH EQU 48 - MAX_DIMMS_PER_SOCKET EQU 16 - - - ; Interface Parameter Structures - ; DMI Type4 - Processor ID -TYPE4_PROC_ID STRUCT - ProcIdLsd UINT32 ? ; < Lower half of 64b ID - ProcIdMsd UINT32 ? ; < Upper half of 64b ID -TYPE4_PROC_ID ENDS - - ; DMI Type 4 - Processor information -TYPE4_DMI_INFO STRUCT - T4ProcType UINT8 ? ; < CPU Type - T4ProcFamily UINT8 ? ; < Family 1 - T4ProcId TYPE4_PROC_ID {} ; < Id - T4Voltage UINT8 ? ; < Voltage - T4ExternalClock UINT16 ? ; < External clock - T4MaxSpeed UINT16 ? ; < Max speed - T4CurrentSpeed UINT16 ? ; < Current speed - T4Status UINT8 ? ; < Status - T4ProcUpgrade UINT8 ? ; < Up grade - T4CoreCount UINT8 ? ; < Core count - T4CoreEnabled UINT8 ? ; < Core Enable - T4ThreadCount UINT8 ? ; < Thread count - T4ProcCharacteristics UINT16 ? ; < Characteristics - T4ProcFamily2 UINT16 ? ; < Family 2 - T4ProcVersion CHAR8 (PROC_VERSION_LENGTH) DUP (?) ; < Cpu version -TYPE4_DMI_INFO ENDS - - ; DMI Type 7 - Cache information -TYPE7_DMI_INFO STRUCT - T7CacheCfg UINT16 ? ; < Cache cfg - T7MaxCacheSize UINT16 ? ; < Max size - T7InstallSize UINT16 ? ; < Install size - T7SupportedSramType UINT16 ? ; < Supported Sram Type - T7CurrentSramType UINT16 ? ; < Current type - T7CacheSpeed UINT8 ? ; < Speed - T7ErrorCorrectionType UINT8 ? ; < ECC type - T7SystemCacheType UINT8 ? ; < Cache type - T7Associativity UINT8 ? ; < Associativity -TYPE7_DMI_INFO ENDS - - ; DMI Type 16 offset 04h - Location - - OtherLocation EQU 01h ; < Assign 01 to Other - UnknownLocation EQU 2 ; < Assign 02 to Unknown - SystemboardOrMotherboard EQU 3 ; < Assign 03 to systemboard or motherboard - IsaAddonCard EQU 4 ; < Assign 04 to ISA add-on card - EisaAddonCard EQU 5 ; < Assign 05 to EISA add-on card - PciAddonCard EQU 6 ; < Assign 06 to PCI add-on card - McaAddonCard EQU 7 ; < Assign 07 to MCA add-on card - PcmciaAddonCard EQU 8 ; < Assign 08 to PCMCIA add-on card - ProprietaryAddonCard EQU 9 ; < Assign 09 to proprietary add-on card - NuBus EQU 10 ; < Assign 0A to NuBus - Pc98C20AddonCard EQU 11 ; < Assign 0A0 to PC-98/C20 add-on card - Pc98C24AddonCard EQU 12 ; < Assign 0A1 to PC-98/C24 add-on card - Pc98EAddoncard EQU 13 ; < Assign 0A2 to PC-98/E add-on card - Pc98LocalBusAddonCard EQU 14 ; < Assign 0A3 to PC-98/Local bus add-on card -DMI_T16_LOCATION TEXTEQU <DWORD> ;} DMI_T16_LOCATION; - - ; DMI Type 16 offset 05h - Memory Error Correction - - OtherUse EQU 01h ; < Assign 01 to Other - UnknownUse EQU 2 ; < Assign 02 to Unknown - SystemMemory EQU 3 ; < Assign 03 to system memory - VideoMemory EQU 4 ; < Assign 04 to video memory - FlashMemory EQU 5 ; < Assign 05 to flash memory - NonvolatileRam EQU 6 ; < Assign 06 to non-volatile RAM - CacheMemory EQU 7 ; < Assign 07 to cache memory -DMI_T16_USE TEXTEQU <DWORD> ;} DMI_T16_USE; - - ; DMI Type 16 offset 07h - Maximum Capacity - - Dmi16OtherErrCorrection EQU 01h ; < Assign 01 to Other - Dmi16UnknownErrCorrection EQU 2 ; < Assign 02 to Unknown - Dmi16NoneErrCorrection EQU 3 ; < Assign 03 to None - Dmi16Parity EQU 4 ; < Assign 04 to parity - Dmi16SingleBitEcc EQU 5 ; < Assign 05 to Single-bit ECC - Dmi16MultiBitEcc EQU 6 ; < Assign 06 to Multi-bit ECC - Dmi16Crc EQU 7 ; < Assign 07 to CRC -DMI_T16_ERROR_CORRECTION TEXTEQU <DWORD> ;} DMI_T16_ERROR_CORRECTION; - - ; DMI Type 16 - Physical Memory Array -TYPE16_DMI_INFO STRUCT - Location DMI_T16_LOCATION ? ; < The physical location of the Memory Array, - ; < whether on the system board or an add-in board. - Use DMI_T16_USE ? ; < Identifies the function for which the array - ; < is used. - MemoryErrorCorrection DMI_T16_ERROR_CORRECTION ? ; < The primary hardware error correction or - ; < detection method supported by this memory array. - MaximumCapacity UINT32 ? ; < The maximum memory capacity, in kilobytes, - ; < for the array. - NumberOfMemoryDevices UINT16 ? ; < The number of slots or sockets available - ; < for memory devices in this array. -TYPE16_DMI_INFO ENDS - - ; DMI Type 17 offset 0Eh - Form Factor - OtherFormFactor EQU 01h ; < Assign 01 to Other - UnknowFormFactor EQU 2 ; < Assign 02 to Unknown - SimmFormFactor EQU 3 ; < Assign 03 to SIMM - SipFormFactor EQU 4 ; < Assign 04 to SIP - ChipFormFactor EQU 5 ; < Assign 05 to Chip - DipFormFactor EQU 6 ; < Assign 06 to DIP - ZipFormFactor EQU 7 ; < Assign 07 to ZIP - ProprietaryCardFormFactor EQU 8 ; < Assign 08 to Proprietary Card - DimmFormFactorFormFactor EQU 9 ; < Assign 09 to DIMM - TsopFormFactor EQU 10 ; < Assign 10 to TSOP - RowOfChipsFormFactor EQU 11 ; < Assign 11 to Row of chips - RimmFormFactor EQU 12 ; < Assign 12 to RIMM - SodimmFormFactor EQU 13 ; < Assign 13 to SODIMM - SrimmFormFactor EQU 14 ; < Assign 14 to SRIMM - FbDimmFormFactor EQU 15 ; < Assign 15 to FB-DIMM -DMI_T17_FORM_FACTOR TEXTEQU <DWORD> - - ; DMI Type 17 offset 12h - Memory Type - OtherMemType EQU 01h ; < Assign 01 to Other - UnknownMemType EQU 2 ; < Assign 02 to Unknown - DramMemType EQU 3 ; < Assign 03 to DRAM - EdramMemType EQU 4 ; < Assign 04 to EDRAM - VramMemType EQU 5 ; < Assign 05 to VRAM - SramMemType EQU 6 ; < Assign 06 to SRAM - RamMemType EQU 7 ; < Assign 07 to RAM - RomMemType EQU 8 ; < Assign 08 to ROM - FlashMemType EQU 9 ; < Assign 09 to Flash - EepromMemType EQU 10 ; < Assign 10 to EEPROM - FepromMemType EQU 11 ; < Assign 11 to FEPROM - EpromMemType EQU 12 ; < Assign 12 to EPROM - CdramMemType EQU 13 ; < Assign 13 to CDRAM - ThreeDramMemType EQU 14 ; < Assign 14 to 3DRAM - SdramMemType EQU 15 ; < Assign 15 to SDRAM - SgramMemType EQU 16 ; < Assign 16 to SGRAM - RdramMemType EQU 17 ; < Assign 17 to RDRAM - DdrMemType EQU 18 ; < Assign 18 to DDR - Ddr2MemType EQU 19 ; < Assign 19 to DDR2 - Ddr2FbdimmMemType EQU 20 ; < Assign 20 to DDR2 FB-DIMM - Ddr3MemType EQU 24 ; < Assign 24 to DDR3 - Fbd2MemType EQU 25 ; < Assign 25 to FBD2 -DMI_T17_MEMORY_TYPE TEXTEQU <DWORD> - - ; DMI Type 17 offset 13h - Type Detail -DMI_T17_TYPE_DETAIL STRUCT - Reserved1 UINT16 ? -; OUT UINT16 Reserved1:1; ; < Reserved -; OUT UINT16 Other:1; ; < Other -; OUT UINT16 Unknown:1; ; < Unknown -; OUT UINT16 FastPaged:1; ; < Fast-Paged -; OUT UINT16 StaticColumn:1; ; < Static column -; OUT UINT16 PseudoStatic:1; ; < Pseudo-static -; OUT UINT16 Rambus:1; ; < RAMBUS -; OUT UINT16 Synchronous:1; ; < Synchronous -; OUT UINT16 Cmos:1; ; < CMOS -; OUT UINT16 Edo:1; ; < EDO -; OUT UINT16 WindowDram:1; ; < Window DRAM -; OUT UINT16 CacheDram:1; ; < Cache Dram -; OUT UINT16 NonVolatile:1; ; < Non-volatile -; OUT UINT16 Reserved2:3; ; < Reserved -DMI_T17_TYPE_DETAIL ENDS - - ; DMI Type 17 - Memory Device -TYPE17_DMI_INFO STRUCT - TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits. - DataWidth UINT16 ? ; < Data Width, in bits, of this memory device. - MemorySize UINT16 ? ; < The size of the memory device. - FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device. - DeviceSet UINT8 ? ; < Identifies when the Memory Device is one of a set of - ; < Memory Devices that must be populated with all devices of - ; < the same type and size, and the set to which this device belongs. - DeviceLocator CHAR8 (8) DUP (?) ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located. - BankLocator CHAR8 (10) DUP (?) ; < The string number of the string that identifies the physically labeled bank where the memory device is located. - MemoryType DMI_T17_MEMORY_TYPE ? ; < The type of memory used in this device. - TypeDetail DMI_T17_TYPE_DETAIL {} ; < Additional detail on the memory device type - Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz). - ManufacturerIdCode UINT64 ? ; < Manufacturer ID code. - SerialNumber CHAR8 (9) DUP (?) ; < Serial Number. - PartNumber CHAR8 (19) DUP (?) ; < Part Number. - Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank. - ExtSize UINT32 ? ; < Extended Size. -TYPE17_DMI_INFO ENDS - - ; Memory DMI Type 17 and 20 - for memory use -MEM_DMI_INFO STRUCT - TotalWidth UINT16 ? ; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. - DataWidth UINT16 ? ; ///< Data Width, in bits, of this memory device. - MemorySize UINT16 ? ; ///< The size of the memory device. - FormFactor DMI_T17_FORM_FACTOR ? ; ///< The implementation form factor for this memory device. - DeviceLocator UINT8 ? ; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. - BankLocator UINT8 ? ; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. - Speed UINT16 ? ; ///< Identifies the speed of the device, in megahertz (MHz). - ManufacturerIdCode UINT64 ? ; ///< Manufacturer ID code. - SerialNumber UINT8 (4) DUP (?) ; ///< Serial Number. - PartNumber UINT8 (18) DUP (?) ; ///< Part Number. - Attributes UINT8 ? ; ///< Bits 7-4: Reserved, Bits 3-0: rank. - ExtSize UINT32 ? ; ///< Extended Size. - Socket UINT8 ? -; OUT UINT8 Socket:3 ; ///< Socket ID -; OUT UINT8 Channel:2 ; ///< Channel ID -; OUT UINT8 Dimm:2 ; ///< DIMM ID -; OUT UINT8 DimmPresent:1 ; ///< Dimm Present - StartingAddr UINT32 ? ; ///< The physical address, in kilobytes, of a range - ; ///< of memory mapped to the referenced Memory Device. - EndingAddr UINT32 ? ; ///< The handle, or instance number, associated with - ; ///< the Memory Device structure to which this address - ; ///< range is mapped. -MEM_DMI_INFO ENDS - - ; DMI Type 19 - Memory Array Mapped Address -TYPE19_DMI_INFO STRUCT - StartingAddr UINT32 ? ; < The physical address, in kilobytes, - ; < of a range of memory mapped to the - ; < specified physical memory array. - EndingAddr UINT32 ? ; < The physical ending address of the - ; < last kilobyte of a range of addresses - ; < mapped to the specified physical memory array. - MemoryArrayHandle UINT16 ? ; < The handle, or instance number, associated - ; < with the physical memory array to which this - ; < address range is mapped. - PartitionWidth UINT8 ? ; < Identifies the number of memory devices that - ; < form a single row of memory for the address - ; < partition defined by this structure. -TYPE19_DMI_INFO ENDS - -; DMI Type 20 - Memory Device Mapped Address -TYPE20_DMI_INFO STRUCT - StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range - ; < of memory mapped to the referenced Memory Device. - EndingAddr UINT32 ? ; < The handle, or instance number, associated with - ; < the Memory Device structure to which this address - ; < range is mapped. - MemoryDeviceHandle UINT16 ? ; < The handle, or instance number, associated with - ; < the Memory Device structure to which this address - ; < range is mapped. - MemoryArrayMappedAddressHandle UINT16 ? ; < The handle, or instance number, associated - ; < with the Memory Array Mapped Address structure to - ; < which this device address range is mapped. - PartitionRowPosition UINT8 ? ; < Identifies the position of the referenced Memory - ; < Device in a row of the address partition. - InterleavePosition UINT8 ? ; < The position of the referenced Memory Device in - ; < an interleave. - InterleavedDataDepth UINT8 ? ; < The maximum number of consecutive rows from the - ; < referenced Memory Device that are accessed in a - ; < single interleaved transfer. -TYPE20_DMI_INFO ENDS - - ; Collection of pointers to the DMI records -DMI_INFO STRUCT - T4 TYPE4_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 4 struc - T7L1 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 1 - T7L2 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 2 - T7L3 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 3 - T16 TYPE16_DMI_INFO {} ; < Type 16 struc - T17 TYPE17_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 17 struc - T19 TYPE19_DMI_INFO {} ; < Type 19 struc - T20 TYPE20_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 20 struc -DMI_INFO ENDS - - - -; ********************************************************************* -; * Interface call: AllocateExecutionCache -; ********************************************************************* - MAX_CACHE_REGIONS EQU 3 - - ; AllocateExecutionCache sub param structure for cached memory region -EXECUTION_CACHE_REGION STRUCT - ExeCacheStartAddr UINT32 ? ; < Start address - ExeCacheSize UINT32 ? ; < Size -EXECUTION_CACHE_REGION ENDS - -; ********************************************************************* -; * Interface call: AmdGetAvailableExeCacheSize -; ********************************************************************* - ; Get available Cache remain -AMD_GET_EXE_SIZE_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Standard header - AvailableExeCacheSize UINT32 ? ; < Remain size -AMD_GET_EXE_SIZE_PARAMS ENDS - - - - - - - ; Selection type for core leveling - CORE_LEVEL_LOWEST EQU 0 ; < Level to lowest common denominator - CORE_LEVEL_TWO EQU 1 ; < Level to 2 cores - CORE_LEVEL_POWER_OF_TWO EQU 2 ; < Level to 1,2,4 or 8 - CORE_LEVEL_NONE EQU 3 ; < Do no leveling - CORE_LEVEL_COMPUTE_UNIT EQU 4 ; < Level cores to one core per compute unit - CORE_LEVEL_ONE EQU 5 ; < Level to 1 core - CORE_LEVEL_THREE EQU 6 ; < Level to 3 cores - CORE_LEVEL_FOUR EQU 7 ; < Level to 4 cores - CORE_LEVEL_FIVE EQU 8 ; < Level to 5 cores - CORE_LEVEL_SIX EQU 9 ; < Level to 6 cores - CORE_LEVEL_SEVEN EQU 10 ; < Level to 7 cores - CORE_LEVEL_EIGHT EQU 11 ; < Level to 8 cores - CORE_LEVEL_NINE EQU 12 ; < Level to 9 cores - CORE_LEVEL_TEN EQU 13 ; < Level to 10 cores - CORE_LEVEL_ELEVEN EQU 14 ; < Level to 11 cores - CORE_LEVEL_TWELVE EQU 15 ; < Level to 12 cores - CORE_LEVEL_THIRTEEN EQU 16 ; < Level to 13 cores - CORE_LEVEL_FOURTEEN EQU 17 ; < Level to 14 cores - CORE_LEVEL_FIFTEEN EQU 18 ; < Level to 15 cores - CoreLevelModeMax EQU 19 ; < Used for bounds checking -CORE_LEVELING_TYPE TEXTEQU <DWORD> - - -; *********************************************************************** -; * -; * AGESA Basic Level interface structure definition and function prototypes -; * -; ********************************************************************** - -; ********************************************************************* -; * Interface call: AmdCreateStruct -; ********************************************************************* - -; ********************************************************************* -; * Interface call: AmdReleaseStruct -; ********************************************************************* - -; ********************************************************************* -; * Interface call: AmdInitReset -; ********************************************************************* - ; AmdInitReset param structure -AMD_RESET_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Standard header - CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region - HtConfig AMD_HT_RESET_INTERFACE {} ; < The interface for Ht Recovery -AMD_RESET_PARAMS ENDS - -; ********************************************************************* -; * Interface call: AmdInitEarly -; ********************************************************************* - ; InitEarly param structure - - ; Provide defaults or customizations to each service performed in AmdInitEarly. - -AMD_EARLY_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < The standard header - CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < Execution Map Interface - PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics. - HtConfig AMD_HT_INTERFACE {} ; < HyperTransport Interface - GnbConfig GNB_CONFIGURATION {} ; < GNB configuration -AMD_EARLY_PARAMS ENDS - -; ********************************************************************* -; * Interface call: AmdInitPost -; ********************************************************************* - ; AmdInitPost param structure -AMD_POST_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Standard header - PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics. - MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param -AMD_POST_PARAMS ENDS - -; ********************************************************************* -; * Interface call: AmdInitEnv -; ********************************************************************* - ; AmdInitEnv param structure -AMD_ENV_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Standard header - PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics. - GnbEnvConfiguration GNB_ENV_CONFIGURATION {} ; < platform operational characteristics. -AMD_ENV_PARAMS ENDS - -; ********************************************************************* -; * Interface call: AmdInitMid -; ********************************************************************* - ; AmdInitMid param structure -AMD_MID_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Standard header - PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics. -AMD_MID_PARAMS ENDS - -; ********************************************************************* -; * Interface call: AmdInitLate -; ********************************************************************* - ; AmdInitLate param structure -AMD_LATE_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Standard header - PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics. - DmiTable POINTER ? ; < DMI Interface - AcpiPState POINTER ? ; < Acpi Pstate SSDT Table - AcpiSrat POINTER ? ; < SRAT Table - AcpiSlit POINTER ? ; < SLIT Table - AcpiWheaMce POINTER ? ; < WHEA MCE Table - AcpiWheaCmc POINTER ? ; < WHEA CMC Table - AcpiAlib POINTER ? ; < ALIB Table -AMD_LATE_PARAMS ENDS - -; ********************************************************************* -; * Interface call: AmdInitRecovery -; ********************************************************************* - ; CPU Recovery Parameters -AMD_CPU_RECOVERY_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Standard Header - PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics -AMD_CPU_RECOVERY_PARAMS ENDS - - ; AmdInitRecovery param structure -AMD_RECOVERY_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Standard header - MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param - CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region. And the max cache region is 3 - CpuRecoveryParams AMD_CPU_RECOVERY_PARAMS {} ; < Params for CPU related recovery init. -AMD_RECOVERY_PARAMS ENDS - - -; ********************************************************************* -; * Interface call: AmdInitResume -; ********************************************************************* - ; AmdInitResume param structure -AMD_RESUME_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Standard header - PlatformConfig PLATFORM_CONFIGURATION {} ; < Platform operational characteristics - S3DataBlock AMD_S3_PARAMS {} ; < Save state data -AMD_RESUME_PARAMS ENDS - -; ********************************************************************* -; * Interface call: AmdS3LateRestore -; ********************************************************************* - ; AmdS3LateRestore param structure -AMD_S3LATE_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Standard header - PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics. - S3DataBlock AMD_S3_PARAMS {} ; < Save state data -AMD_S3LATE_PARAMS ENDS - -; ********************************************************************* -; * Interface call: AmdS3Save -; ********************************************************************* - ; AmdS3Save param structure -AMD_S3SAVE_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Standard header - PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics. - S3DataBlock AMD_S3_PARAMS {} ; < Standard header -AMD_S3SAVE_PARAMS ENDS - - ; General Services API - - -; ********************************************************************* -; * Interface service call: AmdGetApicId -; ********************************************************************* - ; Request the APIC ID of a particular core. - -AMD_APIC_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services. - Socket UINT8 ? ; < The Core's Socket. - Core UINT8 ? ; < The Core id. - IsPresent BOOLEAN ? ; < The Core is present, and ApicAddress is valid. - ApicAddress UINT8 ? ; < The Core's APIC ID. -AMD_APIC_PARAMS ENDS - -; ********************************************************************* -; * Interface service call: AmdGetPciAddress -; ********************************************************************* - ; Request the PCI Address of a Processor Module (that is, its Northbridge) - -AMD_GET_PCI_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services. - Socket UINT8 ? ; < The Processor's socket - Module UINT8 ? ; < The Module in that Processor - IsPresent BOOLEAN ? ; < The Core is present, and PciAddress is valid. - PciAddress PCI_ADDR {} ; < The Processor's PCI Config Space address (Function 0, Register 0) -AMD_GET_PCI_PARAMS ENDS - -; ********************************************************************* -; * Interface service call: AmdIdentifyCore -; ********************************************************************* - ; Request the identity (Socket, Module, Core) of the current Processor Core - -AMD_IDENTIFY_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services. - Socket UINT8 ? ; < The current Core's Socket - Module UINT8 ? ; < The current Core's Processor Module - Core UINT8 ? ; < The current Core's core id. -AMD_IDENTIFY_PARAMS ENDS - -; ********************************************************************* -; * Interface service call: AmdReadEventLog -; ********************************************************************* - ; An Event Log Entry. -EVENT_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services. - EventClass UINT32 ? ; < The severity of this event, matches AGESA_STATUS. - EventInfo UINT32 ? ; < The unique event identifier, zero means "no event". - DataParam1 UINT32 ? ; < Data specific to the Event. - DataParam2 UINT32 ? ; < Data specific to the Event. - DataParam3 UINT32 ? ; < Data specific to the Event. - DataParam4 UINT32 ? ; < Data specific to the Event. -EVENT_PARAMS ENDS - -; ********************************************************************* -; * Interface service call: AmdIdentifyDimm -; ********************************************************************* - ; Request the identity of dimm from system address - -AMD_IDENTIFY_DIMM STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services. - MemoryAddress UINT64 ? ; < System Address that needs to be translated to dimm identification. - SocketId UINT8 ? ; < The socket on which the targeted address locates. - MemChannelId UINT8 ? ; < The channel on which the targeted address locates. - DimmId UINT8 ? ; < The dimm on which the targeted address locates. -AMD_IDENTIFY_DIMM ENDS - - ; Data structure for the Mapping Item between Unified ID for IDS Setup Option - ; and the option value. - -IDS_NV_ITEM STRUCT - IdsNvId UINT16 ? ; < Unified ID for IDS Setup Option. - IdsNvValue UINT16 ? ; < The value of IDS Setup Option. -IDS_NV_ITEM ENDS - - ; Data Structure for IDS CallOut Function -IDS_CALLOUT_STRUCT STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < The Standard Header for AGESA Service - IdsNvPtr POINTER ? ; < Memory Pointer of IDS NV Table - Reserved UINT32 ? ; < reserved -IDS_CALLOUT_STRUCT ENDS - - AGESA_IDS_DFT_VAL EQU 0FFFFh; < Default value of every uninitlized NV item, the action for it will be ignored - AGESA_IDS_NV_END EQU 0FFFFh; < Flag specify end of option structure -; WARNING: Don't change the comment below, it used as signature for script -; AGESA IDS NV ID Definitions - AGESA_IDS_EXT_ID_START EQU 0000h; < specify the start of external NV id - - AGESA_IDS_NV_UCODE EQU 0001h; < Enable or disable microcode patching - - AGESA_IDS_NV_TARGET_PSTATE EQU 0002h; < Set the P-state required to be activated - AGESA_IDS_NV_POSTPSTATE EQU 0003h; < Set the P-state required to be activated through POST - - AGESA_IDS_NV_BANK_INTERLEAVE EQU 0004h; < Enable or disable Bank Interleave - AGESA_IDS_NV_CHANNEL_INTERLEAVE EQU 0005h; < Enable or disable Channel Interleave - AGESA_IDS_NV_NODE_INTERLEAVE EQU 0006h; < Enable or disable Node Interleave - AGESA_IDS_NV_MEMHOLE EQU 0007h; < Enables or disable memory hole - - AGESA_IDS_NV_SCRUB_REDIRECTION EQU 0008h; < Enable or disable a write to dram with corrected data - AGESA_IDS_NV_DRAM_SCRUB EQU 0009h; < Set the rate of background scrubbing for DRAM - AGESA_IDS_NV_DCACHE_SCRUB EQU 000Ah; < Set the rate of background scrubbing for the DCache. - AGESA_IDS_NV_L2_SCRUB EQU 000Bh; < Set the rate of background scrubbing for the L2 cache - AGESA_IDS_NV_L3_SCRUB EQU 000Ch; < Set the rate of background scrubbing for the L3 cache - AGESA_IDS_NV_ICACHE_SCRUB EQU 000Dh; < Set the rate of background scrubbing for the Icache - AGESA_IDS_NV_SYNC_ON_ECC_ERROR EQU 000Eh; < Enable or disable the sync flood on un-correctable ECC error - AGESA_IDS_NV_ECC_SYMBOL_SIZE EQU 000Fh; < Set ECC symbol size - - AGESA_IDS_NV_ALL_MEMCLKS EQU 0010h; < Enable or disable all memory clocks enable - AGESA_IDS_NV_DCT_GANGING_MODE EQU 0011h; < Set the Ganged mode - AGESA_IDS_NV_DRAM_BURST_LENGTH32 EQU 0012h; < Set the DRAM Burst Length 32 - AGESA_IDS_NV_MEMORY_POWER_DOWN EQU 0013h; < Enable or disable Memory power down mode - AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE EQU 0014h; < Set the Memory power down mode - AGESA_IDS_NV_DLL_SHUT_DOWN EQU 0015h; < Enable or disable DLLShutdown - AGESA_IDS_NV_ONLINE_SPARE EQU 0016h; < Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap - - AGESA_IDS_NV_HT_ASSIST EQU 0017h; < Enable or Disable HT Assist - AGESA_IDS_NV_ATMMODE EQU 0018h; < Enable or Disable ATM mode - - AGESA_IDS_NV_HDTOUT EQU 0019h; < Enable or disable HDTOUT feature - - AGESA_IDS_NV_HTLINKSOCKET EQU 001Ah; < HT Link Socket - AGESA_IDS_NV_HTLINKPORT EQU 001Bh; < HT Link Port - AGESA_IDS_NV_HTLINKFREQ EQU 001Ch; < HT Link Frequency - AGESA_IDS_NV_HTLINKWIDTHIN EQU 001Dh; < HT Link In Width - AGESA_IDS_NV_HTLINKWIDTHOUT EQU 001Eh; < HT Link Out Width - - AGESA_IDS_NV_GNBHDAUDIOEN EQU 001Fh; < Enable or disable GNB HD Audio - - AGESA_IDS_NV_CPB_EN EQU 0020h; < Core Performance Boost - - AGESA_IDS_NV_HTC_EN EQU 0021h; < HTC Enable - AGESA_IDS_NV_HTC_OVERRIDE EQU 0022h; < HTC Override - AGESA_IDS_NV_HTC_PSTATE_LIMIT EQU 0023h; < HTC P-state limit select - AGESA_IDS_NV_HTC_TEMP_HYS EQU 0024h; < HTC Temperature Hysteresis - AGESA_IDS_NV_HTC_ACT_TEMP EQU 0025h; < HTC Activation Temp - - AGESA_IDS_NV_POWER_POLICY EQU 0026h; < Select Platform Power Policy - AGESA_IDS_EXT_ID_END EQU 0027h; < specify the end of external NV ID - - IDS_EX_NV_ID TEXTEQU <DWORD> diff --git a/src/vendorcode/amd/agesa/Legacy/amd.inc b/src/vendorcode/amd/agesa/Legacy/amd.inc deleted file mode 100644 index b7162024e4..0000000000 --- a/src/vendorcode/amd/agesa/Legacy/amd.inc +++ /dev/null @@ -1,461 +0,0 @@ -; **************************************************************************** -; * -; * @file -; * -; * Agesa structures and definitions -; * -; * Contains AMD AGESA core interface -; * -; * @xrefitem bom "File Content Label" "Release Content" -; * @e project: AGESA -; * @e sub-project: Include -; * @e \$Revision: 33891 $ @e \$Date: 2010-06-26 00:22:54 +0800 (Sat, 26 Jun 2010) $ -; -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** - - -UINT64 TEXTEQU <QWORD> -UINT32 TEXTEQU <DWORD> -UINT16 TEXTEQU <WORD> -UINT8 TEXTEQU <BYTE> -CHAR8 TEXTEQU <BYTE> -BOOLEAN TEXTEQU <BYTE> -POINTER TEXTEQU <DWORD> - - ; AGESA Types and Definitions - - AGESA_REVISION EQU "Arch2008" - AGESA_ID EQU "AGESA" - - LAST_ENTRY EQU 0FFFFFFFFh - IMAGE_SIGNATURE EQU 'DMA$' - IOCF8 EQU 0CF8h - IOCFC EQU 0CFCh - - ; The return status for all AGESA public services. - - ; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK - ; will have log entries with more detail. - - AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged. - AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested. - ; < Not logged. - AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided. - ; < Example, memory address not installed, heap buffer handle not found. - ; < Not Logged. - ; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available. - AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function. - ; < See log. Example, HT CRC. - AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log. - AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log. - AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log. - AGESA_FATAL EQU 7 ; < Halt booting. See Log. - AgesaStatusMax EQU 8 ; < Not a status, use for limit checking. -AGESA_STATUS TEXTEQU <DWORD> - -; For checking whether a status is at or above the mandatory log level. -AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT - - CALLOUT_ENTRY TEXTEQU <POINTER> - IMAGE_ENTRY TEXTEQU <POINTER> - MODULE_ENTRY TEXTEQU <POINTER> - -; This allocation type is used by the AmdCreateStruct entry point - PreMemHeap EQU 0 ; < Create heap in cache. - PostMemDram EQU 1 ; < Create heap in memory. - ByHost EQU 2 ; < Create heap by Host. -ALLOCATION_METHOD TEXTEQU <DWORD> - - ; These width descriptors are used by the library function, and others, to specify the data size - AccessWidth8 EQU 1 ; < Access width is 8 bits. - AccessWidth16 EQU 2 ; < Access width is 16 bits. - AccessWidth32 EQU 3 ; < Access width is 32 bits. - AccessWidth64 EQU 4 ; < Access width is 64 bits. - - AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data. - AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data. - AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data. - AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data. -ACCESS_WIDTH TEXTEQU <DWORD> - - ; AGESA struct name - - ; AGESA BASIC FUNCTIONS - AMD_INIT_RECOVERY EQU 00020000h - AMD_CREATE_STRUCT EQU 00020001h - AMD_INIT_EARLY EQU 00020002h - AMD_INIT_ENV EQU 00020003h - AMD_INIT_LATE EQU 00020004h - AMD_INIT_MID EQU 00020005h - AMD_INIT_POST EQU 00020006h - AMD_INIT_RESET EQU 00020007h - AMD_INIT_RESUME EQU 00020008h - AMD_RELEASE_STRUCT EQU 00020009h - AMD_S3LATE_RESTORE EQU 0002000Ah - AMD_S3_SAVE EQU 0002000Bh - AMD_GET_APIC_ID EQU 0002000Ch - AMD_GET_PCI_ADDRESS EQU 0002000Dh - AMD_IDENTIFY_CORE EQU 0002000Eh - AMD_READ_EVENT_LOG EQU 0002000Fh - AMD_GET_EXECACHE_SIZE EQU 00020010h - AMD_LATE_RUN_AP_TASK EQU 00020011h - AMD_IDENTIFY_DIMMS EQU 00020012h -AGESA_STRUCT_NAME TEXTEQU <DWORD> - - - ; ResetType constant values - WARM_RESET_WHENEVER EQU 1 - COLD_RESET_WHENEVER EQU 2 - WARM_RESET_IMMEDIATELY EQU 3 - COLD_RESET_IMMEDIATELY EQU 4 - - - ; AGESA Structures - - ; The standard header for all AGESA services. -AMD_CONFIG_PARAMS STRUCT - ImageBasePtr UINT32 ? ; < The AGESA Image base address. - Func UINT32 ? ; < The service desired, @sa dispatch.h. - AltImageBasePtr UINT32 ? ; < Alternate Image location - CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA - HeapStatus UINT8 ? ; < For heap status from boot time slide. - HeapBasePtr UINT64 ? ; < Location of the heap - Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use. -AMD_CONFIG_PARAMS ENDS - - - ; Create Struct Interface. -AMD_INTERFACE_PARAMS STRUCT - StdHeader AMD_CONFIG_PARAMS {} ; < Config header - AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h - AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation - NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only. - NewStructPtr POINTER ? ; < The struct for the service. - ; < The struct to init for ByHost allocation, - ; < the initialized struct on return. -AMD_INTERFACE_PARAMS ENDS - - FUNC_0 EQU 0 ; bit-placed for PCI address creation - FUNC_1 EQU 1 - FUNC_2 EQU 2 - FUNC_3 EQU 3 - FUNC_4 EQU 4 - FUNC_5 EQU 5 - FUNC_6 EQU 6 - FUNC_7 EQU 7 - - ; AGESA Binary module header structure -AMD_IMAGE_HEADER STRUCT - Signature UINT32 ? ; < Binary Signature - CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID - Version CHAR8 (12) DUP (?) ; < 12 characters version - ModuleInfoOffset UINT32 ? ; < Offset of module - EntryPointAddress UINT32 ? ; < Entry address - ImageBase UINT32 ? ; < Image base - RelocTableOffset UINT32 ? ; < Relocate Table offset - ImageSize UINT32 ? ; < Size - Checksum UINT16 ? ; < Checksum - ImageType UINT8 ? ; < Type - V_Reserved UINT8 ? ; < Reserved -AMD_IMAGE_HEADER ENDS - ; AGESA Binary module header structure -AMD_MODULE_HEADER STRUCT - ModuleHeaderSignature UINT32 ? ; < Module signature - ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID - ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version - ModuleDispatcher POINTER ? ; < A pointer point to dispatcher - NextBlock POINTER ? ; < Next module header link -AMD_MODULE_HEADER ENDS - -; AMD_CODE_HEADER Signatures. -AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '> -CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'> -CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'> - -; AGESA_CODE_SIGNATURE -AMD_CODE_HEADER STRUCT - Signature CHAR8 (8) DUP (?) ; < code header Signature - ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module - Version CHAR8 (12) DUP (?) ; < 12 character version string - TerminatorNull CHAR8 ? ; < null terminated string - VerReserved CHAR8 (7) DUP (?) ; < reserved space -AMD_CODE_HEADER ENDS - - ; Extended PCI address format -EXT_PCI_ADDR STRUCT - Register UINT32 ? -; IN OUT UINT32 Register:12; ; < Register offset -; IN OUT UINT32 Function:3; ; < Function number -; IN OUT UINT32 Device:5; ; < Device number -; IN OUT UINT32 Bus:8; ; < Bus number -; IN OUT UINT32 Segment:4; ; < Segment -EXT_PCI_ADDR ENDS - - ; Union type for PCI address -PCI_ADDR UNION - AddressValue UINT32 ? ; < Formal address - Address EXT_PCI_ADDR {} ; < Extended address -PCI_ADDR ENDS - - ; SBDFO - Segment Bus Device Function Offset - ; 31:28 Segment (4-bits) - ; 27:20 Bus (8-bits) - ; 19:15 Device (5-bits) - ; 14:12 Function(3-bits) - ; 11:00 Offset (12-bits) - - - - ILLEGAL_SBDFO EQU 0FFFFFFFFh - - ; CPUID data received registers format -CPUID_DATA STRUCT - EAX_Reg UINT32 ? ; < CPUID instruction result in EAX - EBX_Reg UINT32 ? ; < CPUID instruction result in EBX - ECX_Reg UINT32 ? ; < CPUID instruction result in ECX - EDX_Reg UINT32 ? ; < CPUID instruction result in EDX -CPUID_DATA ENDS - - ; HT frequency for external callbacks -;typedef enum { - HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks - HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks - HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks - HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks - HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks - HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks - HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks - HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks - HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks - HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks - HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks - HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks - HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks - HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks - HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks - HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks - HT_FREQUENCY_MAX EQU 20 ; < Limit Check. -HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES; - -HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M - -IFNDEF BIT0 - BIT0 EQU 0000000000000001h -ENDIF -IFNDEF BIT1 - BIT1 EQU 0000000000000002h -ENDIF -IFNDEF BIT2 - BIT2 EQU 0000000000000004h -ENDIF -IFNDEF BIT3 - BIT3 EQU 0000000000000008h -ENDIF -IFNDEF BIT4 - BIT4 EQU 0000000000000010h -ENDIF -IFNDEF BIT5 - BIT5 EQU 0000000000000020h -ENDIF -IFNDEF BIT6 - BIT6 EQU 0000000000000040h -ENDIF -IFNDEF BIT7 - BIT7 EQU 0000000000000080h -ENDIF -IFNDEF BIT8 - BIT8 EQU 0000000000000100h -ENDIF -IFNDEF BIT9 - BIT9 EQU 0000000000000200h -ENDIF -IFNDEF BIT10 - BIT10 EQU 0000000000000400h -ENDIF -IFNDEF BIT11 - BIT11 EQU 0000000000000800h -ENDIF -IFNDEF BIT12 - BIT12 EQU 0000000000001000h -ENDIF -IFNDEF BIT13 - BIT13 EQU 0000000000002000h -ENDIF -IFNDEF BIT14 - BIT14 EQU 0000000000004000h -ENDIF -IFNDEF BIT15 - BIT15 EQU 0000000000008000h -ENDIF -IFNDEF BIT16 - BIT16 EQU 0000000000010000h -ENDIF -IFNDEF BIT17 - BIT17 EQU 0000000000020000h -ENDIF -IFNDEF BIT18 - BIT18 EQU 0000000000040000h -ENDIF -IFNDEF BIT19 - BIT19 EQU 0000000000080000h -ENDIF -IFNDEF BIT20 - BIT20 EQU 0000000000100000h -ENDIF -IFNDEF BIT21 - BIT21 EQU 0000000000200000h -ENDIF -IFNDEF BIT22 - BIT22 EQU 0000000000400000h -ENDIF -IFNDEF BIT23 - BIT23 EQU 0000000000800000h -ENDIF -IFNDEF BIT24 - BIT24 EQU 0000000001000000h -ENDIF -IFNDEF BIT25 - BIT25 EQU 0000000002000000h -ENDIF -IFNDEF BIT26 - BIT26 EQU 0000000004000000h -ENDIF -IFNDEF BIT27 - BIT27 EQU 0000000008000000h -ENDIF -IFNDEF BIT28 - BIT28 EQU 0000000010000000h -ENDIF -IFNDEF BIT29 - BIT29 EQU 0000000020000000h -ENDIF -IFNDEF BIT30 - BIT30 EQU 0000000040000000h -ENDIF -IFNDEF BIT31 - BIT31 EQU 0000000080000000h -ENDIF -IFNDEF BIT32 - BIT32 EQU 0000000100000000h -ENDIF -IFNDEF BIT33 - BIT33 EQU 0000000200000000h -ENDIF -IFNDEF BIT34 - BIT34 EQU 0000000400000000h -ENDIF -IFNDEF BIT35 - BIT35 EQU 0000000800000000h -ENDIF -IFNDEF BIT36 - BIT36 EQU 0000001000000000h -ENDIF -IFNDEF BIT37 - BIT37 EQU 0000002000000000h -ENDIF -IFNDEF BIT38 - BIT38 EQU 0000004000000000h -ENDIF -IFNDEF BIT39 - BIT39 EQU 0000008000000000h -ENDIF -IFNDEF BIT40 - BIT40 EQU 0000010000000000h -ENDIF -IFNDEF BIT41 - BIT41 EQU 0000020000000000h -ENDIF -IFNDEF BIT42 - BIT42 EQU 0000040000000000h -ENDIF -IFNDEF BIT43 - BIT43 EQU 0000080000000000h -ENDIF -IFNDEF BIT44 - BIT44 EQU 0000100000000000h -ENDIF -IFNDEF BIT45 - BIT45 EQU 0000200000000000h -ENDIF -IFNDEF BIT46 - BIT46 EQU 0000400000000000h -ENDIF -IFNDEF BIT47 - BIT47 EQU 0000800000000000h -ENDIF -IFNDEF BIT48 - BIT48 EQU 0001000000000000h -ENDIF -IFNDEF BIT49 - BIT49 EQU 0002000000000000h -ENDIF -IFNDEF BIT50 - BIT50 EQU 0004000000000000h -ENDIF -IFNDEF BIT51 - BIT51 EQU 0008000000000000h -ENDIF -IFNDEF BIT52 - BIT52 EQU 0010000000000000h -ENDIF -IFNDEF BIT53 - BIT53 EQU 0020000000000000h -ENDIF -IFNDEF BIT54 - BIT54 EQU 0040000000000000h -ENDIF -IFNDEF BIT55 - BIT55 EQU 0080000000000000h -ENDIF -IFNDEF BIT56 - BIT56 EQU 0100000000000000h -ENDIF -IFNDEF BIT57 - BIT57 EQU 0200000000000000h -ENDIF -IFNDEF BIT58 - BIT58 EQU 0400000000000000h -ENDIF -IFNDEF BIT59 - BIT59 EQU 0800000000000000h -ENDIF -IFNDEF BIT60 - BIT60 EQU 1000000000000000h -ENDIF -IFNDEF BIT61 - BIT61 EQU 2000000000000000h -ENDIF -IFNDEF BIT62 - BIT62 EQU 4000000000000000h -ENDIF -IFNDEF BIT63 - BIT63 EQU 8000000000000000h -ENDIF - diff --git a/src/vendorcode/amd/agesa/Legacy/bridge32.inc b/src/vendorcode/amd/agesa/Legacy/bridge32.inc deleted file mode 100644 index 8685c6c077..0000000000 --- a/src/vendorcode/amd/agesa/Legacy/bridge32.inc +++ /dev/null @@ -1,577 +0,0 @@ -; **************************************************************************** -; * -; * @file -; * -; * Agesa structures and definitions -; * -; * Contains AMD AGESA core interface -; * -; * @xrefitem bom "File Content Label" "Release Content" -; * @e project: AGESA -; * @e sub-project: Include -; * @e \$Revision: 23714 $ @e \$Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $ -; -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** - -PARAM1 textequ <[bp+8]> -PARAM2 textequ <[bp+12]> -PARAM3 textequ <[bp+16]> -RETAddress textequ <[bp+4]> - -AMD_PRIVATE_PARAMS STRUCT - Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16 - Gate16_SS DW ? ; RM stack segment - Router_Seg DW ? ; Segment of oem router - Router_Off DW ? ; Offset of oem router -AMD_PRIVATE_PARAMS ENDS - -; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults. -IFNDEF AGESA_SELECTOR_GDT - AGESA_SELECTOR_GDT EQU 00h -ENDIF -IFNDEF AGESA_SELECTOR_CODE16 - AGESA_SELECTOR_CODE16 EQU 08h -ENDIF -IFNDEF AGESA_SELECTOR_DATA16 - AGESA_SELECTOR_DATA16 EQU 10h -ENDIF -IFNDEF AGESA_SELECTOR_CODE32 - AGESA_SELECTOR_CODE32 EQU 18h -ENDIF -IFNDEF AGESA_SELECTOR_DATA32 - AGESA_SELECTOR_DATA32 EQU 20h -ENDIF - - -AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ - - GDT_Name LABEL BYTE - DD 000000000h, 000000000h ; NULL descriptor - DD 00000ffffh, 000009b00h ; 16-bit code, fixed up - DD 00000ffffh, 000009300h ; 16-bit data, fixed up - DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code - DD 00000ffffh, 000CF9300h ; 32-bit protected mode data - GDT_Length EQU ($-GDT_Name) - -ENDM - -;+------------------------------------------------------------------------- -; -; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface -; -; Processing: -; The following steps are taken: -; 1) Enter 32bit Protected Mode (PM32) -; 2) Run AGESA code -; 3) Restore Real Mode (RM) -; -; Entry: -; [big real mode] : ds, es set to base 0 limit 4G segment -; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset) -; ESI - configuration block pointer -; -; Exit: -; EAX - return value -; ESI - configuration block pointer -; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode -; -; Modified: -; None -; - -AMD_BRIDGE_32 MACRO GDT_Name - - local copyGDT - local flushTo16PM - local agesaReturnAddress - local leave32bitPM - local flush2RM - - push gs - push fs - push ebx - push ecx - push edi - mov eax, esp - push eax - movzx esp, sp -; -; Do not use any locals here, BP will be changed frequently during RM->PM32->RM -; - pushf - cli ; Disable interrupts during AGESA - cld ; Need known direction flag during AGESA - -; -; Save the FAR PTR input parameter -; - mov gs, dx ; Offset - shr edx, 16 - mov fs, dx ; Segment -; -; Determine where our binary file is and get entry point -; - mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr - add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress -; -; Figure out the return address we will use after calling AGESA -; and store it in ebx until we have our stack set up properly -; - mov ebx, cs - shl ebx, 4 - add ebx, OFFSET agesaReturnAddress -; -; Save our current RM stack AND entry EBP -; - push ebp -; push esp - push ss - -; -; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN -; -; Copy the GDT onto the stack for modification -; - mov cx, GDT_Length - sub sp, cx - mov bp, sp - lea di, GDT_Name -copyGDT: - mov al, cs:[di] - mov [bp], al - inc di - inc bp - loop copyGDT -; -; Patch 16-bit code and data descriptors on stack. We will -; fix up CS and SS for PM16 during the callout if applicable. -; - mov bp, sp - - mov eax, cs - shl eax, 4 - mov [bp+AGESA_SELECTOR_CODE16+2], ax - shr eax, 16 - mov [bp+AGESA_SELECTOR_CODE16+4], al - - mov eax, ss - shl eax, 4 - mov [bp+AGESA_SELECTOR_DATA16+2], ax - shr eax, 16 - mov [bp+AGESA_SELECTOR_DATA16+4], al -; -; Need to place Length and Address on GDT -; - mov eax, ss - shl eax, 4 - add eax, esp - push eax - push WORD PTR (GDT_Length-1) -; -; Load the GDT -; - mov bp, sp - lgdt FWORD PTR [bp] -; -; TABLE 1 -; -; Place PRIVATE DATA on stack DIRECTLY following GDT -; During this routine, stack data is critical. If -; order is changed or additional added, bad things -; will happen! -; -; HIGHEST PHYSICAL ADDRESS -; -; | ... | -; ------------------------ -; | old RM SP | -; | old RM SS | -; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address}) -; | GDT_DATA32 | -; | ... | -; | GDT_NULL | -; | GDT Addr, Length | -; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS -; | Priv.Gate16_SS | -; | Priv.Gate16_CS | -; ------------------------ sp -; ------ THEN PUSH ------- -; | Return to 16-bit CS | -; | Return to 16-bit Off | -; | ... | -; -; LOWEST PHYSICAL ADDRESS -; - mov edi, esp - sub edi, SIZEOF AMD_PRIVATE_PARAMS - mov ax, cs - mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax - mov ax, ss - mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax - mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs - mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs - - mov esp, edi -; -; Save an address for returning to 16 bit real mode on stack, -; we'll use it in a far ret after turning off CR0.PE so that -; we can take our address off and force a far jump. Be sure -; no unexpected data is on the stack after this! -; - mov ax, cs - push cs - lea ax, flush2RM - push ax -; -; Convert ss:esp to "flat" -; - - mov ax, sp - push ax - mov eax, ss - shl eax, 4 - add eax, esp - mov esp, eax ; Load the zero based ESP - -; -; Set CR0.PE -; - mov eax, CR0 ; Get CPU control word 0 - or al, 01 ; Enable CPU protected mode - mov CR0, eax ; Write back to CPU control word 0 - jmp flushTo16PM - -flushTo16PM: -; -; 16-bit protected mode -; - mov ax, AGESA_SELECTOR_DATA32 - mov ds, ax - mov es, ax - mov fs, ax - mov gs, ax - mov ss, ax -; -; Push our parameters RIGHT TO LEFT, and then return address -; - push esi ; AGESA configuration block pointer (data) - push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret - pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat) - push edx ; AGESA entry point (32PM flat) - - DB 066h - retf ; <><><> Enter AGESA 32-bit code!!! <><><> - -agesaReturnAddress: -; -; Returns from the Agesa 32-bit code still PM32 -; - DB 0EAh - DD OFFSET leave32bitPM - DW AGESA_SELECTOR_CODE16 - -leave32bitPM: -; -; Now in 16-bit PM -; - add esp, 4 ; +4 to remove our config block pointer -; -; Eax reserve AGESA_STATUS return code, save it -; - mov ebx, eax -; -; Turn off CR0.PE, restore 64K stack limit -; - pop ax - mov sp, ax - mov ax, AGESA_SELECTOR_DATA16 - mov ss, ax - - mov eax, CR0 - and al, NOT 1 ; Disable protected mode - mov CR0, eax ; Write back CR0.PE -; -; Jump far to enter RM, we saved this address on the stack -; already. Hopefully stack is balanced through AGESA -; nor were any params added by pushing them on the stack and -; not removing them between BEGIN-END comments. -; - retf - -flush2RM: -; -; Set segments registers for big real mode before returning -; - xor ax, ax - mov ds, ax - mov es, ax - mov fs, ax - mov gs, ax -; -; Discard GDT, +6 for GDT pointer/size, privates -; - add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS -; -; Restore real mode stack and entry EBP -; - pop cx -; mov esp, [esp] - mov ss, cx - pop ebp -; -; Restore AGESA_STATUS return code to eax -; - mov eax, ebx -; -; END --- STACK MUST BE BALANCED TO THIS POINT --- END -; - - popf - pop ebx - mov esp, ebx - pop edi - pop ecx - pop ebx - pop fs - pop gs - ; EXIT AMD_BRIDGE_32 -ENDM -;+------------------------------------------------------------------------- -; -; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface -; -; Processing: -; The following steps are taken: -; 1) Enter PM16 -; 2) Setup stack, get private params -; 3) Enter RM -; 4) Get 3 params -; 5) Call oemCallout OR oem router -; 6) Enter PM32 -; 7) Return to Agesa PH -; -; Entry: -; [32-bit protected mode] -; [esp+8] Func -; [esp+12] Data -; [esp+16] Configuration Block -; [esp+4] return address to Agesa -; -; Exit: -; [32-bit protected mode] -; -; Modified: -; None -; -AMD_CALLOUT_16 MACRO LocalOemCalloutRouter -; -; Note that we are still PM32, so MASM may work strangely -; - - push bp ; Save our original SP to access params - mov bp, sp - push bx - push si - push di - push cx - push dx - push di - - DB 066h, 0EAh - DW OFFSET PM16Entry - DW AGESA_SELECTOR_CODE16 - -PM16Entry: -; -; PM16 CS, but still PM32 SS, as we need to access our private params -; before we enter RM. -; -; Note: we are working below the stack temporarily, and and it will -; not affect our ability to get entry params -; - xor ecx, ecx - xor edx, edx -; -; SGDT will give us the original location of the GDT on our CAS stack. -; We need this value because our private parameters are located just -; below the GDT. -; - mov edi, esp - sub edi, GDT_Length + 6 - sgdt FWORD PTR [edi] ; [edi] = word size, dword address - mov edi, DWORD PTR [edi+2] ; Get the PM32 address only - sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6 -; -; cx = code segment of this code in RM -; dx = stack segment of CAS in RM -; fs = code segment of oem router (save for later) -; gs = offset of oem router (save for later) -; fs and gs are loaded after switch to real mode because we can't -; use them as scratch pad registers in protected mode -; - mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS - mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS - - mov eax, edi ; Save edi in eax for after RM switch - mov edi, esp ; Save our current ESP for RM - - movzx ebx, dx - shl ebx, 4 - sub esp, ebx - -; -; We had been accessing the stack in PM32, we will now change to PM16 so we -; will make the stack segment 64KB limit so SP needs to be fixed made PM16 -; compatible. -; - mov bx, AGESA_SELECTOR_DATA16 - mov ss, bx - -; -; Save the RM segment and RM offset of the jump we will need to make in -; order to enter RM so that code in this segment is relocatable. -; -; BEGIN --- Don't unbalance the stack --- BEGIN -; - push cx - pushw OFFSET RMEntry - - mov ebx, CR0 - and bl, NOT 1 - mov CR0, ebx ; CR0.PE cleared -; -; Far jump to clear segment descriptor cache and enter RM -; - retf - -RMEntry: -; -; We are in RM, setup RM stack -; - movzx ebx, dx ; Get RM SS in ebx - shl ebx, 4 ; Get our stack top on entry in EBP to - sub ebp, ebx ; access our entry parameters - sub eax, ebx ; save copy of parameters address - mov ss, dx ; Set stack segment -; -; We are going to figure out the address to use when we return -; and have to go back into PM32 while we have access to it -; - movzx ebx, cx ; Get original CS in ebx - shl ebx, 4 - add ebx, OFFSET PM32Entry -; -; Now we put our data, func, block params into calling convention -; for our hook -; -; ECX = Func -; EDX = Data -; ESI = config pointer -; - mov ecx, PARAM1 ; Func - mov edx, PARAM2 ; Data - mov esi, PARAM3 ; pointer - - push ebx ; Save PM32 mode switch address - push edi ; Save PM32 stack pointer - pushf -; -; Get Router Function Address -; - mov edi, eax - mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg - mov fs, ax - mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off - mov gs, ax - - mov eax, AGESA_UNSUPPORTED ; Default return value -; -; If AMD_BRIDGE_32 EDX == 0 call oemCallout -; otherwise call FAR PTR EDX -; -; Critical: -; sp+2 - EDI aka PM32 stack address -; sp+4 - address of PM32Entry in PM32 -; - mov bx, fs - shl ebx, 16 - mov bx, gs - - .if (ebx == 0) - call LocalOemCalloutRouter - .else -; -; Make far call to Router function -; - push cs - push offset CalloutReturn - push ebx - retf -CalloutReturn: - .endif -; -; Restore PM32 esp from RM stack -; - popf - pop edi ; Our PM32 stack pointer - pop edx ; Our PM32 mode switch address - - mov ebx, CR0 - or bl, 1 ; CR0.PE set - mov CR0, ebx - - mov ebx, AGESA_SELECTOR_DATA32 - pushd AGESA_SELECTOR_CODE32 ; PM32 selector - push edx ; PM32 entry point - - DB 066h - retf ; Far jump to enter PM32 - -PM32Entry: -; -; END --- Don't unbalance the stack --- END -; We are now PM32, so remember MASM is assembling in 16-bit again -; - mov ss, bx - mov ds, bx - mov es, bx - mov fs, bx - mov gs, bx - - mov sp, di - pop di - pop dx - pop cx - pop di - pop si - pop bx - pop bp - ; EXIT AMD_CALLOUT_16 -ENDM |