diff options
Diffstat (limited to 'src/vboot')
-rw-r--r-- | src/vboot/Kconfig | 7 | ||||
-rw-r--r-- | src/vboot/vboot_common.h | 5 | ||||
-rw-r--r-- | src/vboot/verstage.c | 7 |
3 files changed, 3 insertions, 16 deletions
diff --git a/src/vboot/Kconfig b/src/vboot/Kconfig index e67c108d4a..2b6cde1c19 100644 --- a/src/vboot/Kconfig +++ b/src/vboot/Kconfig @@ -95,13 +95,6 @@ config RETURN_FROM_VERSTAGE reused by the succeeding stage. This is useful if a RAM space is too small to fit both the verstage and the succeeding stage. -config CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL - bool "The chipset provides the main() entry point for verstage" - default n - depends on SEPARATE_VERSTAGE - help - The chipset code provides their own main() entry point. - config VBOOT_DYNAMIC_WORK_BUFFER bool "Vboot's work buffer is dynamically allocated." default y if ARCH_ROMSTAGE_X86_32 && !SEPARATE_VERSTAGE diff --git a/src/vboot/vboot_common.h b/src/vboot/vboot_common.h index 956b54c196..aa01f28944 100644 --- a/src/vboot/vboot_common.h +++ b/src/vboot/vboot_common.h @@ -97,11 +97,10 @@ int vboot_platform_is_resuming(void); /* ============================= VERSTAGE ================================== */ /* - * Main logic for verified boot. verstage() is the stage entry point - * while the verstage_main() is just the core logic. + * Main logic for verified boot. verstage_main() is just the core vboot logic. + * If the verstage is a separate stage, it should be entered via main(). */ void verstage_main(void); -void verstage(void); void verstage_mainboard_init(void); /* Check boot modes */ diff --git a/src/vboot/verstage.c b/src/vboot/verstage.c index 0ec9ca6d27..64fadc736e 100644 --- a/src/vboot/verstage.c +++ b/src/vboot/verstage.c @@ -24,7 +24,7 @@ void __attribute__((weak)) verstage_mainboard_init(void) /* Default empty implementation. */ } -void verstage(void) +void main(void) { console_init(); exception_init(); @@ -37,8 +37,3 @@ void verstage(void) hlt(); } } - -#if !IS_ENABLED(CONFIG_CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL) -/* This is for boards that rely on main() for an entry point of a stage. */ -void main(void) __attribute__((alias ("verstage"))); -#endif |