3 files changed, 14 insertions, 2 deletions
diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc
index ae4b283d3c..b0b7b8c520 100644
--- a/src/superio/winbond/Makefile.inc
+++ b/src/superio/winbond/Makefile.inc
@@ -14,7 +14,7 @@
 ##
 
 ## include generic winbond pre-ram stage driver
-romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_serial.c
+romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_init.c
 
 subdirs-y += w83627dhg
 subdirs-y += w83627ehg
diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_init.c
index aebbd38b46..7c3ce2b3a5 100644
--- a/src/superio/winbond/common/early_serial.c
+++ b/src/superio/winbond/common/early_init.c
@@ -15,7 +15,7 @@
  */
 
 /*
- * A generic romstage (pre-ram) driver for Winbond variant Super I/O chips.
+ * A generic romstage (pre-ram) driver for various Winbond Super I/O chips.
  *
  * The following is derived directly from the vendor Winbond's data-sheets:
  *
@@ -79,3 +79,14 @@ void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t s
 	pnp_write_config(dev, offset, byte);
 	pnp_exit_conf_state(dev);
 }
+
+void winbond_set_clksel_48(pnp_devfn_t dev)
+{
+	u8 reg8;
+
+	pnp_enter_conf_state(dev);
+	reg8 = pnp_read_config(dev, 0x24);
+	reg8 |= (1 << 6); /* Set the clock input to 48MHz. */
+	pnp_write_config(dev, 0x24, reg8);
+	pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h
index 6e67eeb83d..e472018bf1 100644
--- a/src/superio/winbond/common/winbond.h
+++ b/src/superio/winbond/common/winbond.h
@@ -22,6 +22,7 @@
 
 void winbond_enable_serial(pnp_devfn_t dev, uint16_t iobase);
 void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state);
+void winbond_set_clksel_48(pnp_devfn_t dev);
 
 void pnp_enter_conf_state(pnp_devfn_t dev);
 void pnp_exit_conf_state(pnp_devfn_t dev);