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-rw-r--r--src/superio/fintek/f71863fg/Makefile.inc22
-rw-r--r--src/superio/fintek/f71863fg/chip.h30
-rw-r--r--src/superio/fintek/f71863fg/f71863fg.h29
-rw-r--r--src/superio/fintek/f71863fg/f71863fg_early_serial.c46
-rw-r--r--src/superio/fintek/f71863fg/superio.c111
5 files changed, 238 insertions, 0 deletions
diff --git a/src/superio/fintek/f71863fg/Makefile.inc b/src/superio/fintek/f71863fg/Makefile.inc
new file mode 100644
index 0000000000..663f171a8b
--- /dev/null
+++ b/src/superio/fintek/f71863fg/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+obj-$(CONFIG_SUPERIO_FINTEK_F71863FG) += superio.o
+
diff --git a/src/superio/fintek/f71863fg/chip.h b/src/superio/fintek/f71863fg/chip.h
new file mode 100644
index 0000000000..21ac2c6d59
--- /dev/null
+++ b/src/superio/fintek/f71863fg/chip.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <uart8250.h>
+
+/* This chip doesn't have keyboard and mouse support. */
+
+extern struct chip_operations superio_fintek_f71863fg_ops;
+
+struct superio_fintek_f71863fg_config {
+ struct uart8250 com1, com2;
+};
diff --git a/src/superio/fintek/f71863fg/f71863fg.h b/src/superio/fintek/f71863fg/f71863fg.h
new file mode 100644
index 0000000000..bd67b24669
--- /dev/null
+++ b/src/superio/fintek/f71863fg/f71863fg.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Logical Device Numbers (LDN). */
+#define F71863FG_FDC 0x00 /* Floppy */
+#define F71863FG_SP1 0x01 /* UART1 */
+#define F71863FG_SP2 0x02 /* UART2 */
+#define F71863FG_PP 0x03 /* Parallel Port */
+#define F71863FG_HWM 0x04 /* Hardware Monitor */
+#define F71863FG_KBC 0x05 /* KBC devices */
+#define F71863FG_GPIO 0x06 /* General Purpose I/O (GPIO) */
+#define F71863FG_PME 0x0a /* Power Management Events (PME) */
diff --git a/src/superio/fintek/f71863fg/f71863fg_early_serial.c b/src/superio/fintek/f71863fg/f71863fg_early_serial.c
new file mode 100644
index 0000000000..afa9c357af
--- /dev/null
+++ b/src/superio/fintek/f71863fg/f71863fg_early_serial.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Wang Qing Pei<wangqingpei@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */
+
+#include <arch/romcc_io.h>
+#include "f71863fg.h"
+
+static inline void pnp_enter_conf_state(device_t dev)
+{
+ unsigned int port = dev >> 8;
+ outb(0x87, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ unsigned int port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void f71863fg_enable_serial(device_t dev, unsigned int iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c
new file mode 100644
index 0000000000..beed854659
--- /dev/null
+++ b/src/superio/fintek/f71863fg/superio.c
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Wang Qing Pei<wangqingpei@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <stdlib.h>
+#include <uart8250.h>
+#include "chip.h"
+#include "f71863fg.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ outb(0x87, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ outb(0xaa, dev->path.pnp.port);
+}
+
+static void f71863fg_init(device_t dev)
+{
+ struct superio_fintek_f71863fg_config *conf = dev->chip_info;
+ struct resource *res0;
+
+ if (!dev->enabled)
+ return;
+
+ switch(dev->path.pnp.device) {
+ /* TODO: Might potentially need code for HWM or FDC etc. */
+ case F71863FG_SP1:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com1);
+ break;
+ case F71863FG_SP2:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com2);
+ break;
+ }
+}
+
+static void f71863fg_pnp_set_resources(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_resources(dev);
+ pnp_exit_conf_state(dev);
+}
+
+static void f71863fg_pnp_enable_resources(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_enable_resources(dev);
+ pnp_exit_conf_state(dev);
+}
+
+static void f71863fg_pnp_enable(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ (dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
+ pnp_exit_conf_state(dev);
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = f71863fg_pnp_set_resources,
+ .enable_resources = f71863fg_pnp_enable_resources,
+ .enable = f71863fg_pnp_enable,
+ .init = f71863fg_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ /* TODO: Some of the 0x7f8 etc. values may not be correct. */
+ { &ops, F71863FG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, F71863FG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, F71863FG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
+ { &ops, F71863FG_GPIO, PNP_IRQ0, },
+ { &ops, F71863FG_PME, },
+};
+
+static void enable_dev(device_t dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_fintek_f71863fg_ops = {
+ CHIP_NAME("Fintek F71863FG Super I/O")
+ .enable_dev = enable_dev
+};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 11:18:47 +0000