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-rw-r--r--src/southbridge/amd/sb600/Kconfig4
-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig4
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h1
-rw-r--r--src/southbridge/intel/i3100/Kconfig9
-rw-r--r--src/southbridge/intel/i82801ax/i82801ax.h1
-rw-r--r--src/southbridge/intel/i82801bx/i82801bx.h1
-rw-r--r--src/southbridge/intel/i82801dx/i82801dx.h9
-rw-r--r--src/southbridge/intel/i82801dx/lpc.c6
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig5
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h1
-rw-r--r--src/southbridge/intel/sch/Kconfig4
-rw-r--r--src/southbridge/nvidia/ck804/Kconfig4
-rw-r--r--src/southbridge/via/vt8237r/lpc.c8
-rw-r--r--src/southbridge/via/vt8237r/vt8237r.h1
14 files changed, 36 insertions, 22 deletions
diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig
index 8ec396700d..51d8310d22 100644
--- a/src/southbridge/amd/sb600/Kconfig
+++ b/src/southbridge/amd/sb600/Kconfig
@@ -59,4 +59,8 @@ config SATA_MODE
default 1 if SATA_MODE_IDE
default 0 if SATA_MODE_AHCI
+config HPET_MIN_TICKS
+ hex
+ default 0x14
+
endif
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index a7d41dcb84..75858c2a67 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -55,4 +55,8 @@ config SERIRQ_CONTINUOUS_MODE
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
+config HPET_MIN_TICKS
+ hex
+ default 0x80
+
endif
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 7e67e3bbe6..c9044ed1d3 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -47,7 +47,6 @@
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
-#define HPET_ADDR 0xfed00000
#define DEFAULT_RCBA 0xfed1c000
#ifndef __ACPI__
diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig
index f2b7923039..e0acc632f4 100644
--- a/src/southbridge/intel/i3100/Kconfig
+++ b/src/southbridge/intel/i3100/Kconfig
@@ -2,3 +2,12 @@ config SOUTHBRIDGE_INTEL_I3100
bool
select IOAPIC
select HAVE_HARD_RESET
+
+if SOUTHBRIDGE_INTEL_I3100
+
+config HPET_MIN_TICKS
+ hex
+ default 0x90
+
+endif
+
diff --git a/src/southbridge/intel/i82801ax/i82801ax.h b/src/southbridge/intel/i82801ax/i82801ax.h
index bd192e019e..186a917975 100644
--- a/src/southbridge/intel/i82801ax/i82801ax.h
+++ b/src/southbridge/intel/i82801ax/i82801ax.h
@@ -33,7 +33,6 @@ int smbus_read_byte(u8 device, u8 address);
#define SMBUS_IO_BASE 0x0f00
#define PMBASE_ADDR 0x0400
-#define HPET_ADDR 0xfed00000
#define PCI_DMA_CFG 0x90
#define SERIRQ_CNTL 0x64
diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h
index 090cddfbae..405e52baa6 100644
--- a/src/southbridge/intel/i82801bx/i82801bx.h
+++ b/src/southbridge/intel/i82801bx/i82801bx.h
@@ -34,7 +34,6 @@ int smbus_read_byte(u8 device, u8 address);
#define SMBUS_IO_BASE 0x0f00
#define PMBASE_ADDR 0x0400
#define GPIO_BASE_ADDR 0x0500
-#define HPET_ADDR 0xfed00000
#define SECSTS 0x1e
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index 4da430a395..d9e4d3809d 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -41,15 +41,6 @@ int smbus_read_byte(unsigned device, unsigned address);
#endif
#endif
-/*
- * HPET Memory Address Range. Possible values:
- * 0xfed00000 for FED0_0000h - FED0_03FFh
- * 0xfed01000 for FED0_1000h - FED0_13FFh
- * 0xfed02000 for FED0_2000h - FED0_23FFh
- * 0xfed03000 for FED0_3000h - FED0_33FFh
- */
-#define HPET_ADDR 0xfed00000
-
#define DEBUG_PERIODIC_SMIS 0
#define MAINBOARD_POWER_OFF 0
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 768e70096b..fbf8e12228 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -233,7 +233,7 @@ static void enable_hpet(struct device *dev)
u32 reg32, hpet, val;
/* Set HPET base address and enable it */
- printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", HPET_ADDR);
+ printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", CONFIG_HPET_ADDRESS);
reg32 = pci_read_config32(dev, GEN_CNTL);
/*
* Bit 17 is HPET enable bit.
@@ -241,7 +241,7 @@ static void enable_hpet(struct device *dev)
*/
reg32 &= ~(3 << 15); /* Clear it */
- hpet = HPET_ADDR >> 12;
+ hpet = CONFIG_HPET_ADDRESS >> 12;
hpet &= 0x3;
reg32 |= (hpet << 15);
@@ -254,7 +254,7 @@ static void enable_hpet(struct device *dev)
val &= 0x7;
if ((val & 0x4) && (hpet == (val & 0x3))) {
- printk(BIOS_INFO, "HPET enabled at 0x%x\n", HPET_ADDR);
+ printk(BIOS_INFO, "HPET enabled at 0x%x\n", CONFIG_HPET_ADDRESS);
} else {
printk(BIOS_WARNING, "HPET was not enabled correctly\n");
reg32 &= ~(1 << 17); /* Clear Enable */
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 3550954583..4937df7096 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -41,7 +41,10 @@ config USBDEBUG_DEFAULT_PORT
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/i82801gx/bootblock.c"
- depends on SOUTHBRIDGE_INTEL_I82801GX
+
+config HPET_MIN_TICKS
+ hex
+ default 0x80
endif
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 8fb5b92f43..566311f55f 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -32,7 +32,6 @@
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
-#define HPET_ADDR 0xfed00000
#define DEFAULT_RCBA 0xfed1c000
#ifndef __ACPI__
diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig
index 83ff447f3e..32eb8688ec 100644
--- a/src/southbridge/intel/sch/Kconfig
+++ b/src/southbridge/intel/sch/Kconfig
@@ -48,5 +48,9 @@ config CMC_FILE
The path and filename of the file to use as CMC state machine
binary.
+config HPET_MIN_TICKS
+ hex
+ default 0x80
+
endif
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 97927d7a18..b6f718ee1b 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -38,4 +38,8 @@ config CK804_NUM
int
default 1
+config HPET_MIN_TICKS
+ hex
+ default 0xfa
+
endif
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index a47ab38a56..1d96560d03 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -387,8 +387,8 @@ static void vt8237a_init(struct device *dev)
/* Host Bus Power Management Control, maybe not needed */
pci_write_config8(dev, 0x8c, 0x5);
- /* Enable HPET at VT8237R_HPET_ADDR. */
- pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
+ /* Enable HPET */
+ pci_write_config32(dev, 0x68, (CONFIG_HPET_ADDRESS | 0x80));
southbridge_init_common(dev);
@@ -426,8 +426,8 @@ static void vt8237s_init(struct device *dev)
/* Host Bus Power Management Control, maybe not needed */
pci_write_config8(dev, 0x8c, 0x5);
- /* Enable HPET at VT8237R_HPET_ADDR., does not work correctly on R. */
- pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
+ /* Enable HPET, does not work correctly on R. */
+ pci_write_config32(dev, 0x68, (CONFIG_HPET_ADDRESS | 0x80));
southbridge_init_common(dev);
diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h
index 9d5a1fc608..58cb85735a 100644
--- a/src/southbridge/via/vt8237r/vt8237r.h
+++ b/src/southbridge/via/vt8237r/vt8237r.h
@@ -33,7 +33,6 @@
#else
#define VT8237S_SPI_MEM_BASE 0xfed02000UL
#endif
-#define VT8237R_HPET_ADDR 0xfed00000ULL
/* PMBASE FIXME mostly taken from ich7 */
#define PM1_STS 0x00
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 02:17:01 +0000