diff options
Diffstat (limited to 'src/southbridge')
23 files changed, 99 insertions, 39 deletions
diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index ed4072dc2e..5af6b134e0 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -22,3 +22,11 @@ config SOUTHBRIDGE_AMD_SB600 select IOAPIC select HAVE_USBDEBUG +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_AMD_SB600 + +config EHCI_DEBUG_OFFSET + hex + default 0xe0 if SOUTHBRIDGE_AMD_SB600 + diff --git a/src/southbridge/amd/sb600/Makefile.inc b/src/southbridge/amd/sb600/Makefile.inc index b13d3de01f..854539b9b3 100644 --- a/src/southbridge/amd/sb600/Makefile.inc +++ b/src/southbridge/amd/sb600/Makefile.inc @@ -8,3 +8,4 @@ driver-y += sb600_hda.c driver-y += sb600_ac97.c driver-y += sb600_pci.c ramstage-y += sb600_reset.c +romstage-y += sb600_enable_usbdebug.c diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h index 629f389973..0ba107acc7 100644 --- a/src/southbridge/amd/sb600/sb600.h +++ b/src/southbridge/amd/sb600/sb600.h @@ -40,4 +40,5 @@ void sb600_enable(device_t dev); void sb600_lpc_port80(void); void sb600_pci_port80(void); +void sb600_enable_usbdebug(unsigned int port); #endif /* SB600_H */ diff --git a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c b/src/southbridge/amd/sb600/sb600_enable_usbdebug.c index 6a150aded0..b4d97b0da2 100644 --- a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c +++ b/src/southbridge/amd/sb600/sb600_enable_usbdebug.c @@ -18,12 +18,11 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> - -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */ -#define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */ +#include "sb600.h" /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) @@ -31,7 +30,7 @@ void set_debug_port(unsigned int port) /* TODO: Allow changing the physical USB port used as Debug Port. */ } -static void sb600_enable_usbdebug(unsigned int port) +void sb600_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ @@ -39,7 +38,7 @@ static void sb600_enable_usbdebug(unsigned int port) set_debug_port(port); /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 5ceb446a82..97768d18e5 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -27,3 +27,11 @@ config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT default n depends on SOUTHBRIDGE_AMD_SB700 +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_AMD_SB700 + +config EHCI_DEBUG_OFFSET + hex + default 0xe0 if SOUTHBRIDGE_AMD_SB700 + diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc index 8e6868bb17..dd97df31e6 100644 --- a/src/southbridge/amd/sb700/Makefile.inc +++ b/src/southbridge/amd/sb700/Makefile.inc @@ -7,3 +7,4 @@ driver-y += sb700_sata.c driver-y += sb700_hda.c driver-y += sb700_pci.c ramstage-y += sb700_reset.c +romstage-y += sb700_enable_usbdebug.c diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index d4107a942e..088bba611d 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -59,4 +59,5 @@ void sb700_setup_sata_phys(struct device *dev); #endif +void sb700_enable_usbdebug(unsigned int port); #endif /* SB700_H */ diff --git a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c index 02d3900047..d74a9bbc9f 100644 --- a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c +++ b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c @@ -19,14 +19,13 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "sb700.h" -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */ -#define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */ - -#define EHCI_EOR (EHCI_BAR + 0x20) +#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) #define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) void set_debug_port(unsigned int port) @@ -46,12 +45,12 @@ void set_debug_port(unsigned int port) * This code currently only supports the first one, i.e., USB Debug devices * attached to physical USB ports belonging to the first EHCI device. */ -static void sb700_enable_usbdebug(unsigned int port) +void sb700_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 556f526735..afee190b2d 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -24,3 +24,11 @@ config SOUTHBRIDGE_INTEL_I82801GX select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_INTEL_I82801GX + +config EHCI_DEBUG_OFFSET + hex + default 0xa0 if SOUTHBRIDGE_INTEL_I82801GX + diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index b5a2054526..559c896901 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -39,10 +39,13 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 +#if !defined(ASSEMBLY) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); #endif +void i82801gx_enable_usbdebug(unsigned int port); +#endif #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c index 464dac2b92..991aa5adaa 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c +++ b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c @@ -18,12 +18,12 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> - -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 /* Hardwired 0x10 (>= ICH4). */ -#define EHCI_DEBUG_OFFSET 0xA0 /* Hardwired 0xa0 (>= ICH5). */ +#include "i82801gx.h" /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) @@ -31,20 +31,20 @@ void set_debug_port(unsigned int port) /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ } -static void i82801gx_enable_usbdebug(unsigned int port) +void i82801gx_enable_usbdebug(unsigned int port) { u32 dbgctl; device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Force ownership of the Debug Port to the EHCI controller. */ printk(BIOS_DEBUG, "Enabling OWNER_CNT\n"); - dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET); + dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); dbgctl |= (1 << 30); - write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl); + write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); } diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index f0cfae7183..d4a8650708 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -8,3 +8,11 @@ config ID_SECTION_OFFSET hex default 0x80 if SOUTHBRIDGE_NVIDIA_CK804 +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_NVIDIA_CK804 + +config EHCI_DEBUG_OFFSET + hex + default 0x98 if SOUTHBRIDGE_NVIDIA_CK804 + diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index bceec85737..48f7713a8b 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -15,5 +15,8 @@ ramstage-y += ck804_reset.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ck804_fadt.c +romstage-y += ck804_enable_usbdebug.c + chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds + diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h index fb1b8d80a0..7285d18d0e 100644 --- a/src/southbridge/nvidia/ck804/ck804.h +++ b/src/southbridge/nvidia/ck804/ck804.h @@ -4,5 +4,6 @@ #include "chip.h" void ck804_enable(device_t dev); +void ck804_enable_usbdebug(unsigned int port); #endif diff --git a/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c b/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c index f82196329e..3cccded343 100644 --- a/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c @@ -22,8 +22,11 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "ck804.h" #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE @@ -31,10 +34,6 @@ #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 -#define EHCI_DEBUG_OFFSET 0x98 - void set_debug_port(unsigned int port) { u32 dword; @@ -47,7 +46,7 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -static void ck804_enable_usbdebug(unsigned int port) +void ck804_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ @@ -55,7 +54,7 @@ static void ck804_enable_usbdebug(unsigned int port) set_debug_port(port); /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index 213b1755f9..6084b1ea44 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -6,3 +6,12 @@ config SOUTHBRIDGE_NVIDIA_MCP55 config ID_SECTION_OFFSET hex default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55 + +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_NVIDIA_MCP55 + +config EHCI_DEBUG_OFFSET + hex + default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55 + diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 4388ca8e9a..a9dcf7f40f 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -15,5 +15,7 @@ driver-$(CONFIG_GENERATE_ACPI_TABLES) += mcp55_fadt.c ramstage-y += mcp55_reset.c +romstage-y += mcp55_enable_usbdebug.c + chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 687232f302..acb291a1d0 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -29,4 +29,5 @@ void mcp55_enable(device_t dev); #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif +void mcp55_enable_usbdebug(unsigned int port); #endif /* MCP55_H */ diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c index f1f5c2ab11..e0b293c81a 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c @@ -22,8 +22,11 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "mcp55.h" #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE @@ -31,10 +34,6 @@ #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 -#define EHCI_DEBUG_OFFSET 0x98 - void set_debug_port(unsigned int port) { u32 dword; @@ -47,7 +46,7 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -static void mcp55_enable_usbdebug(unsigned int port) +void mcp55_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ @@ -55,7 +54,7 @@ static void mcp55_enable_usbdebug(unsigned int port) set_debug_port(port); /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index f84f1506fb..bbb5ee971b 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -6,3 +6,11 @@ config SOUTHBRIDGE_SIS_SIS966 config ID_SECTION_OFFSET hex default 0x80 if SOUTHBRIDGE_SIS_SIS966 + +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 + +config EHCI_DEBUG_OFFSET + hex + default 0x98 if SOUTHBRIDGE_SIS_SIS966 diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index c3f000c769..e51c81fa83 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -9,6 +9,7 @@ driver-y += sis966_sata.c driver-y += sis966_pcie.c driver-y += sis966_aza.c ramstage-y += sis966_reset.c +romstage-y += sis966_enable_usbdebug.c chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.lds diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h index ee04a65878..324beef3c9 100644 --- a/src/southbridge/sis/sis966/sis966.h +++ b/src/southbridge/sis/sis966/sis966.h @@ -32,5 +32,6 @@ #include "chip.h" void sis966_enable(device_t dev); +void sis966_enable_usbdebug(unsigned int port); #endif /* SIS966_H */ diff --git a/src/southbridge/sis/sis966/sis966_enable_usbdebug.c b/src/southbridge/sis/sis966/sis966_enable_usbdebug.c index 64aa7be277..a82e941b3a 100644 --- a/src/southbridge/sis/sis966/sis966_enable_usbdebug.c +++ b/src/southbridge/sis/sis966/sis966_enable_usbdebug.c @@ -24,8 +24,11 @@ /* TODO: Check whether this actually works (might be copy-paste leftover). */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "sis966.h" #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE @@ -33,10 +36,6 @@ #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 -#define EHCI_DEBUG_OFFSET 0x98 - void set_debug_port(unsigned int port) { u32 dword; @@ -49,7 +48,7 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -static void sis966_enable_usbdebug(unsigned int port) +void sis966_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ @@ -57,7 +56,7 @@ static void sis966_enable_usbdebug(unsigned int port) set_debug_port(port); /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |